Corrected v := r_rst.

libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd

@@ -104,6 +104,7 @@ ARCHITECTURE str OF fringe_stop_unit IS
   SIGNAL dbg_lookup_imag_dc   : INTEGER := common_math_sum_look_up_table(c_lookup_imag);
   
   SIGNAL r, rin               : reg_type;
+  SIGNAL r_rst                : reg_type := ((OTHERS=>c_dp_sosi_rst), (OTHERS=>'0'), '0', '0', '0', '0', '0');
   
   SIGNAL wr_offset_last       : STD_LOGIC;  
   SIGNAL wr_offset_last_dp    : STD_LOGIC;  
@@ -166,7 +167,7 @@ BEGIN
     END IF; 
     
     IF dp_rst = '1' THEN 
-      v.flush_accu := '0';
+      v := r_rst;
     END IF;
     
     rin <= v;