From 22fab3fc7ea8de9d57623866757e97f050bd4d62 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 4 Oct 2017 05:52:41 +0000
Subject: [PATCH] Corrected v := r_rst.
---
libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
index 71df89ddd5..2be2173700 100644
--- a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
@@ -104,6 +104,7 @@ ARCHITECTURE str OF fringe_stop_unit IS
SIGNAL dbg_lookup_imag_dc : INTEGER := common_math_sum_look_up_table(c_lookup_imag);
SIGNAL r, rin : reg_type;
+ SIGNAL r_rst : reg_type := ((OTHERS=>c_dp_sosi_rst), (OTHERS=>'0'), '0', '0', '0', '0', '0');
SIGNAL wr_offset_last : STD_LOGIC;
SIGNAL wr_offset_last_dp : STD_LOGIC;
@@ -166,7 +167,7 @@ BEGIN
END IF;
IF dp_rst = '1' THEN
- v.flush_accu := '0';
+ v := r_rst;
END IF;
rin <= v;
--
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