-Finished first generation of wrapper code.

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/myhdl/gen_mms_diag_block_gen.py

@@ -39,10 +39,23 @@ Remarks:
   falls outside of the myHDL scope.
   . We use separate DP signals for now, but we may also combine them into a
     Python record as this is fully supported my myHDL.
+Usage:
+. python gen_mms_diag_block_gen.py
+. VHDL files are generated in the same dir.
 """
 
 from myhdl import *
 
+###############################################################################
+# Constants/generics
+# . NOTE: use extra quotes around strings!
+###############################################################################
+G_NOF_STREAMS = 4
+G_BUF_DAT_W = 16
+G_BUF_ADDR_W = 256
+G_FILE_NAME_PREFIX = '"hex/bg_data"' # Note: extra quotes
+G_DIAG_BLOCK_GEN_RST = '"FIXME"'     # Note: extra quotes
+
 ###############################################################################
 # MyHDL function definition
 # . VHDL entity I/O ports
@@ -52,9 +65,9 @@ from myhdl import *
 #   . Not described here (pass). We set the .vhdl_code attribute later on to 
 #     insert literal VHDL.
 ###############################################################################
-def myhdl_mms_diag_block_gen_wrap(mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr):
+def myhdl_mms_diag_block_gen(g_nof_streams, g_buf_dat_w, g_buf_addr_w, g_file_name_prefix, g_diag_block_gen_rst, mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr):
 
-    @always(dp_clk)
+    @always(mm_rst,mm_clk,dp_rst,dp_clk)
     def wrap():
         # Nothing to do here.
         pass
@@ -67,30 +80,41 @@ def myhdl_mms_diag_block_gen_wrap(mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr):
 
 ###############################################################################
 # Architecture VHDL code: Instantiate mms_diag_block_gen
+# . Note the $ prefix for all myHDL function (myhdl_mms_diag_block_gen)
+#   arguments.
 ###############################################################################
-myhdl_mms_diag_block_gen_wrap.vhdl_code =\
+myhdl_mms_diag_block_gen.vhdl_code =\
 """
   u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
   GENERIC MAP (
-    g_nof_streams        => 4,
-    g_buf_dat_w          => 16,
-    g_buf_addr_w         => 256,
-    g_file_name_prefix   => "hex/bg_data",
-    g_diag_block_gen_rst => c_bg_ctrl
+    g_nof_streams        => $g_nof_streams,
+    g_buf_dat_w          => $g_buf_dat_w,
+    g_buf_addr_w         => $g_buf_addr_w,
+    g_file_name_prefix   => $g_file_name_prefix,
+    g_diag_block_gen_rst => $g_diag_block_gen_rst
   )
   PORT MAP (
-    mm_rst           => mm_rst,
-    mm_clk           => mm_clk,
+    mm_rst           => $mm_rst,
+    mm_clk           => $mm_clk,
   
-    dp_rst           => dp_rst,
-    dp_clk           => dp_clk,
+    dp_rst           => $dp_rst,
+    dp_clk           => $dp_clk,
 
-    out_sosi_arr     => out_sosi_arr
+    out_sosi_arr     => $out_sosi_arr
   );
 """
 
 ###############################################################################
 # Convert to VHDL
 ###############################################################################
-toVHDL(myhdl_mms_diag_block_gen_wrap,mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr)
+mm_clk = Signal(bool(0))
+mm_rst = Signal(bool(0))
+dp_clk = Signal(bool(0))
+dp_rst = Signal(bool(0))
+out_sosi_arr = Signal(intbv(0)[8:]) #FIXME
+
+toVHDL(myhdl_mms_diag_block_gen, G_NOF_STREAMS, G_BUF_DAT_W, G_BUF_ADDR_W, G_FILE_NAME_PREFIX, G_DIAG_BLOCK_GEN_RST,mm_rst,mm_clk,dp_rst,dp_clk,out_sosi_arr)
+
+
+