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Commit 2181acda authored by Reinier van der Walle's avatar Reinier van der Walle
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added a reverse word option to dp_block_from_mm and used it in

statistics_offload
parent 3cc91b3b
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1 merge request!118added a reverse word option to dp_block_from_mm and used it in
...@@ -272,7 +272,8 @@ BEGIN ...@@ -272,7 +272,8 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_data_size => c_data_size, g_data_size => c_data_size,
g_step_size => c_step_size, g_step_size => c_step_size,
g_nof_data => c_nof_data g_nof_data => c_nof_data,
g_reverse_word_order => TRUE -- default word order is MSB after LSB, we need to stream LSB after MSB.
) )
PORT MAP( PORT MAP(
dp_rst => dp_rst, dp_rst => dp_rst,
......
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
-- -------------------------------------------------------------------------- -- --------------------------------------------------------------------------
-- Author: -- Author:
-- . Pieter Donker -- . Pieter Donker, R van der Walle
-- Purpose: -- Purpose:
-- . Read a block of data from memory mapped (MM) location and stream it as a block of data. -- . Read a block of data from memory mapped (MM) location and stream it as a block of data.
-- Description: -- Description:
...@@ -36,7 +36,8 @@ ENTITY dp_block_from_mm IS ...@@ -36,7 +36,8 @@ ENTITY dp_block_from_mm IS
GENERIC ( GENERIC (
g_data_size : NATURAL; g_data_size : NATURAL;
g_step_size : NATURAL; g_step_size : NATURAL;
g_nof_data : NATURAL g_nof_data : NATURAL;
g_reverse_word_order : BOOLEAN := FALSE
); );
PORT ( PORT (
rst : IN STD_LOGIC; rst : IN STD_LOGIC;
...@@ -55,6 +56,7 @@ END dp_block_from_mm; ...@@ -55,6 +56,7 @@ END dp_block_from_mm;
ARCHITECTURE rtl OF dp_block_from_mm IS ARCHITECTURE rtl OF dp_block_from_mm IS
CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data; CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data;
CONSTANT c_word_index_rst : NATURAL := sel_a_b(g_reverse_word_order, g_data_size - 1, 0);
TYPE t_reg IS RECORD TYPE t_reg IS RECORD
busy : STD_LOGIC; busy : STD_LOGIC;
...@@ -64,7 +66,7 @@ ARCHITECTURE rtl OF dp_block_from_mm IS ...@@ -64,7 +66,7 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
step_index : NATURAL; step_index : NATURAL;
END RECORD; END RECORD;
CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0); CONSTANT c_reg_rst : t_reg := ('0', '0', '0', c_word_index_rst, 0);
SIGNAL r : t_reg; SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg; SIGNAL nxt_r : t_reg;
...@@ -111,6 +113,23 @@ BEGIN ...@@ -111,6 +113,23 @@ BEGIN
IF out_siso.ready = '1' THEN IF out_siso.ready = '1' THEN
-- continue with block -- continue with block
mm_mosi.rd <= '1'; mm_mosi.rd <= '1';
IF g_reverse_word_order THEN
IF r.word_index > 0 THEN
v.word_index := r.word_index - 1;
ELSE
v.word_index := g_data_size - 1;
v.step_index := r.step_index + g_step_size;
END IF;
-- check start of block
IF r.word_index = g_data_size - 1 AND r.step_index = 0 THEN
v.sop := '1';
END IF;
ELSE
IF r.word_index < g_data_size - 1 THEN IF r.word_index < g_data_size - 1 THEN
v.word_index := r.word_index + 1; v.word_index := r.word_index + 1;
ELSE ELSE
...@@ -123,13 +142,23 @@ BEGIN ...@@ -123,13 +142,23 @@ BEGIN
v.sop := '1'; v.sop := '1';
END IF; END IF;
END IF;
-- check end of block -- check end of block
IF mm_address >= last_mm_address THEN IF g_reverse_word_order THEN
IF mm_address = last_mm_address - (g_data_size - 1) THEN -- with reversed word order the last word to read is actually the first word of the last step index
v.eop := '1';
-- prepare for next block
v.busy := '0';
v.step_index := 0;
v.word_index := g_data_size - 1;
END IF;
ELSIF mm_address >= last_mm_address THEN -- g_reverse_word_order = False
v.eop := '1'; v.eop := '1';
-- prepare for next block -- prepare for next block
v.busy := '0'; v.busy := '0';
v.word_index := 0;
v.step_index := 0; v.step_index := 0;
v.word_index := 0;
END IF; END IF;
END IF; END IF;
END IF; END IF;
......
...@@ -37,7 +37,8 @@ ENTITY dp_block_from_mm_dc IS ...@@ -37,7 +37,8 @@ ENTITY dp_block_from_mm_dc IS
GENERIC ( GENERIC (
g_data_size : NATURAL; g_data_size : NATURAL;
g_step_size : NATURAL; g_step_size : NATURAL;
g_nof_data : NATURAL g_nof_data : NATURAL;
g_reverse_word_order : BOOLEAN := FALSE
); );
PORT ( PORT (
-- mm_clk domain -- mm_clk domain
...@@ -127,7 +128,8 @@ BEGIN ...@@ -127,7 +128,8 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_data_size => g_data_size, g_data_size => g_data_size,
g_step_size => g_step_size, g_step_size => g_step_size,
g_nof_data => g_nof_data g_nof_data => g_nof_data,
g_reverse_word_order => g_reverse_word_order
) )
PORT MAP ( PORT MAP (
clk => mm_clk, clk => mm_clk,
......
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