using a CLKBUF in betweekn input clock and PLL

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd

@@ -20,7 +20,7 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, technology_lib, tech_pll_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
@@ -35,7 +35,9 @@ USE technology_lib.technology_pkg.ALL;
 
 ENTITY unb2_board_clk125_pll IS
   GENERIC (
-    g_technology : NATURAL := c_tech_arria10
+    g_technology : NATURAL := c_tech_arria10;
+    g_use_clkbuf : BOOLEAN := TRUE;
+    g_use_fpll   : BOOLEAN := FALSE
   );
   PORT (
     arst        : IN  STD_LOGIC := '0';
@@ -51,19 +53,58 @@ END unb2_board_clk125_pll;
 
 
 ARCHITECTURE arria10 OF unb2_board_clk125_pll IS
+
+  SIGNAL clk125buf : STD_LOGIC;
+
 BEGIN
 
+  no_clkbuf : IF g_use_clkbuf=FALSE GENERATE
+    clk125buf <= clk125;
+  END GENERATE;
+  
+  gen_clkbuf : IF g_use_clkbuf=TRUE GENERATE
+    u_clkbuf : ENTITY tech_clkbuf_lib.tech_clkbuf
+    GENERIC MAP (
+      g_technology   => g_technology,
+      g_clock_net    => "GLOBAL"
+    )
+    PORT MAP (
+      inclk  => clk125,
+      outclk => clk125buf
+    );
+  END GENERATE;
+
+
+  gen_pll : IF g_use_fpll=FALSE GENERATE
     u_pll : ENTITY tech_pll_lib.tech_pll_clk125
     GENERIC MAP (
       g_technology => g_technology
     )
     PORT MAP (
       areset  => arst,
-    inclk0  => clk125,
+      inclk0  => clk125buf,
       c0      => c0_clk20,
       c1      => c1_clk50,
       c2      => c2_clk100,
       c3      => c3_clk125,
       locked  => pll_locked
     );
+  END GENERATE;
+
+  --gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
+  --  u_pll : ENTITY tech_pll_lib.tech_pll_clk125
+  --  GENERIC MAP (
+  --    g_technology => g_technology
+  --  )
+  --  PORT MAP (
+  --    areset  => arst,
+  --    inclk0  => clk125buf,
+  --    c0      => c0_clk20,
+  --    c1      => c1_clk50,
+  --    c2      => c2_clk100,
+  --    c3      => c3_clk125,
+  --    locked  => pll_locked
+  --  );
+  --END GENERATE;
+
 END arria10;