From 213aad03592b8bf3df2211e4ca8ecb8f49a68bec Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 26 May 2015 13:59:11 +0000
Subject: [PATCH] using a CLKBUF in betweekn input clock and PLL
---
.../src/vhdl/unb2_board_clk125_pll.vhd | 71 +++++++++++++++----
1 file changed, 56 insertions(+), 15 deletions(-)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index 775017a5c8..54cb709666 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, technology_lib, tech_pll_lib;
+LIBRARY IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
@@ -35,7 +35,9 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2_board_clk125_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10;
+ g_use_clkbuf : BOOLEAN := TRUE;
+ g_use_fpll : BOOLEAN := FALSE
);
PORT (
arst : IN STD_LOGIC := '0';
@@ -51,19 +53,58 @@ END unb2_board_clk125_pll;
ARCHITECTURE arria10 OF unb2_board_clk125_pll IS
+
+ SIGNAL clk125buf : STD_LOGIC;
+
BEGIN
- u_pll : ENTITY tech_pll_lib.tech_pll_clk125
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- areset => arst,
- inclk0 => clk125,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ no_clkbuf : IF g_use_clkbuf=FALSE GENERATE
+ clk125buf <= clk125;
+ END GENERATE;
+
+ gen_clkbuf : IF g_use_clkbuf=TRUE GENERATE
+ u_clkbuf : ENTITY tech_clkbuf_lib.tech_clkbuf
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ PORT MAP (
+ inclk => clk125,
+ outclk => clk125buf
+ );
+ END GENERATE;
+
+
+ gen_pll : IF g_use_fpll=FALSE GENERATE
+ u_pll : ENTITY tech_pll_lib.tech_pll_clk125
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
+ END GENERATE;
+
+ --gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
+ -- u_pll : ENTITY tech_pll_lib.tech_pll_clk125
+ -- GENERIC MAP (
+ -- g_technology => g_technology
+ -- )
+ -- PORT MAP (
+ -- areset => arst,
+ -- inclk0 => clk125buf,
+ -- c0 => c0_clk20,
+ -- c1 => c1_clk50,
+ -- c2 => c2_clk100,
+ -- c3 => c3_clk125,
+ -- locked => pll_locked
+ -- );
+ --END GENERATE;
+
END arria10;
--
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