From 1ecd6b8f97f0b79931eff97edd19cefc17d489e1 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 29 Apr 2016 09:38:53 +0000
Subject: [PATCH] Put IP for 10GbE MAC, PLL and base-R under hdl_lib_uses_ip.
---
libraries/technology/10gbase_r/hdllib.cfg | 39 ++++++++---------------
libraries/technology/mac_10g/hdllib.cfg | 3 +-
libraries/technology/pll/hdllib.cfg | 3 +-
3 files changed, 17 insertions(+), 28 deletions(-)
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 9d9de8bd73..4ad799bc9a 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -1,31 +1,18 @@
hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib
-hdl_lib_uses_synth = technology
- tech_pll
- ip_arria10_phy_10gbase_r
- ip_arria10_phy_10gbase_r_4
- ip_arria10_phy_10gbase_r_12
- ip_arria10_phy_10gbase_r_24
- ip_arria10_phy_10gbase_r_48
- ip_arria10_transceiver_pll_10g
- ip_arria10_transceiver_reset_controller_1
- ip_arria10_transceiver_reset_controller_4
- ip_arria10_transceiver_reset_controller_12
- ip_arria10_transceiver_reset_controller_24
- ip_arria10_transceiver_reset_controller_48
- ip_arria10_e3sge3_phy_10gbase_r
- ip_arria10_e3sge3_phy_10gbase_r_4
- ip_arria10_e3sge3_phy_10gbase_r_12
- ip_arria10_e3sge3_phy_10gbase_r_24
- ip_arria10_e3sge3_phy_10gbase_r_48
- ip_arria10_e3sge3_transceiver_pll_10g
- ip_arria10_e3sge3_transceiver_reset_controller_1
- ip_arria10_e3sge3_transceiver_reset_controller_4
- ip_arria10_e3sge3_transceiver_reset_controller_12
- ip_arria10_e3sge3_transceiver_reset_controller_24
- ip_arria10_e3sge3_transceiver_reset_controller_48
- tech_transceiver
- common
+hdl_lib_uses_synth = technology common tech_pll tech_transceiver
+hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r
+ ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4
+ ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12
+ ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24
+ ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48
+ ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1
+ ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4
+ ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12
+ ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24
+ ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48
+
hdl_lib_uses_sim =
hdl_lib_technology =
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index 840ffab5b6..a4b5a74321 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -1,6 +1,7 @@
hdl_lib_name = tech_mac_10g
hdl_library_clause_name = tech_mac_10g_lib
-hdl_lib_uses_synth = technology ip_stratixiv_mac_10g ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g common dp
+hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g
+hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g
hdl_lib_uses_sim =
hdl_lib_technology =
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index c3a56f5f93..aacb820117 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -1,9 +1,10 @@
hdl_lib_name = tech_pll
hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses_synth = technology common ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_uses_synth = technology common
hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arria10_e3sge3_pll_clk200
ip_stratixiv_pll_clk25 ip_arria10_pll_clk25 ip_arria10_e3sge3_pll_clk25
ip_arria10_pll_clk125 ip_arria10_e3sge3_pll_clk125
+ ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
hdl_lib_uses_sim =
hdl_lib_technology =
--
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