Added tb_tech_eth_10g_ppm.vhd for verifying ppm clock offset between devices,...

Added  tb_tech_eth_10g_ppm.vhd for verifying ppm clock offset between devices, however the eth_10g fails in simualtion.

libraries/technology/eth_10g/hdllib.cfg

@@ -13,6 +13,7 @@ synth_files =
 
 test_bench_files =
     tb_tech_eth_10g.vhd
+    tb_tech_eth_10g_ppm.vhd
     
 modelsim_search_libraries =
     altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver

libraries/technology/eth_10g/tb_tech_eth_10g.vhd

@@ -25,12 +25,11 @@
 --   . proc_tech_mac_10g_rx_packet() for expected header and data type
 --   . tx_pkt_cnt=rx_pkt_cnt > 0 must be true at the tb_end.
 -- Usage:
---   > as 10
+--   > as 14
 --   > run -all
 
 LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib, common_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
@@ -48,9 +47,15 @@ ENTITY tb_tech_eth_10g IS
   -- Test bench control parameters
   GENERIC (
     g_technology              : NATURAL := c_tech_select_default;
-    --   g_data_type = c_tb_tech_mac_10g_data_type_symbols  = 0
-    --   g_data_type = c_tb_tech_mac_10g_data_type_counter  = 1
-    g_data_type  : NATURAL := c_tb_tech_mac_10g_data_type_symbols
+    g_tech_pll_clk_644_period : TIME := tech_pll_clk_644_period;
+    g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
+    g_verify_link_recovery    : BOOLEAN := TRUE;
+    g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
+    g_use_rx_serial_in        : BOOLEAN := FALSE 
+  );
+  PORT (
+    tx_serial_out : OUT STD_LOGIC;
+    rx_serial_in  : IN  STD_LOGIC
   );
 END tb_tech_eth_10g;
 
@@ -121,7 +126,6 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
   -- 10G PHY serial interface
   SIGNAL tx_serial_arr       : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL tx_serial_arr_dly   : STD_LOGIC_VECTOR(0 DOWNTO 0);
-  SIGNAL tx_serial_arr_fault : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL rx_serial_arr       : STD_LOGIC_VECTOR(0 DOWNTO 0);
   
   -- Model a serial link fault
@@ -196,6 +200,7 @@ BEGIN
     proc_common_wait_some_cycles(clk_156, c_pkt_length_arr1(c_nof_pkt1-1)/c_tech_mac_10g_symbols_per_beat);
     proc_common_wait_some_cycles(clk_156, 100);
     
+    IF g_verify_link_recovery=TRUE THEN
       -- Model a link fault to verify Rx recovery
       link_fault <= '1';
       proc_common_wait_some_cycles(clk_156, 1000);
@@ -208,6 +213,8 @@ BEGIN
     
       proc_common_wait_some_cycles(clk_156, c_pkt_length_arr2(c_nof_pkt2-1)/c_tech_mac_10g_symbols_per_beat);
       proc_common_wait_some_cycles(clk_156, 100);
+    END IF;
+    
     tb_end <= '1';
     WAIT;
   END PROCESS;
@@ -274,7 +281,7 @@ BEGIN
   rx_siso_arr(0) <= rx_siso;
   rx_sosi        <= rx_sosi_arr(0);
   
-  tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER tech_pll_clk_644_period/2;
+  tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_tech_pll_clk_644_period/2;
 
   pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
   GENERIC MAP (
@@ -294,6 +301,7 @@ BEGIN
       g_technology          => g_technology,
       g_sim                 => FALSE,
       g_nof_channels        => 1,
+      g_link_status_check   => g_link_status_check,
       --g_pre_header_padding  => FALSE
       g_pre_header_padding  => TRUE
     )
@@ -333,10 +341,15 @@ BEGIN
 
   -- Loopback serial
   tx_serial_arr_dly <= TRANSPORT tx_serial_arr AFTER phy_delay;
+  tx_serial_out <= tx_serial_arr_dly(0);
   
-  p_rx_serial : PROCESS(tx_serial_arr_dly, link_fault)
+  p_rx_serial : PROCESS(tx_serial_arr_dly, rx_serial_in, link_fault)
   BEGIN
+    IF g_use_rx_serial_in=FALSE THEN
       rx_serial_arr <= tx_serial_arr_dly;
+    ELSE
+      rx_serial_arr(0) <= rx_serial_in;
+    END IF;
     IF link_fault='1' THEN
       rx_serial_arr(0) <= '0';
     END IF;
@@ -358,6 +371,7 @@ BEGIN
     ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
       REPORT "Not all transmitted packets were received." SEVERITY ERROR;
     END IF;
+    proc_common_wait_some_cycles(clk_156, 100);
     
     -- Stop the simulation
     ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;

libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench running two tech_eth_10g with ppm offset.
+-- Description:
+--   The two instances of tb_tech_eth_10g have a 100 ppm offset in their
+--   tr_ref_clk_644.
+--   The tb is self checking based on that tb_tech_eth_10g is self checking
+--   and both tb_tech_eth_10g instances send the same and expect the same.
+-- Usage:
+--   > as 14
+--   > run -all
+
+LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib;
+USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_tech_eth_10g_ppm IS
+  -- Test bench control parameters
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default
+  );
+END tb_tech_eth_10g_ppm;
+
+ARCHITECTURE tb OF tb_tech_eth_10g_ppm IS
+
+  SIGNAL tx_serial_0 : STD_LOGIC;
+  SIGNAL tx_serial_1 : STD_LOGIC;
+
+BEGIN
+
+  u_tb_tech_eth_10g_0 : ENTITY work.tb_tech_eth_10g
+  GENERIC MAP (
+    g_technology              => g_technology,
+    g_tech_pll_clk_644_period => tech_pll_clk_644_period - tech_pll_clk_644_10ppm,
+    g_verify_link_recovery    => FALSE,
+    g_link_status_check       => "01",
+    g_use_rx_serial_in        => TRUE
+  )
+  PORT MAP (
+    tx_serial_out => tx_serial_0,
+    rx_serial_in  => tx_serial_1
+  );
+
+  u_tb_tech_eth_10g_1 : ENTITY work.tb_tech_eth_10g
+  GENERIC MAP (
+    g_technology              => g_technology,
+    g_tech_pll_clk_644_period => tech_pll_clk_644_period + tech_pll_clk_644_10ppm,
+    g_verify_link_recovery    => FALSE,
+    g_link_status_check       => "01",
+    g_use_rx_serial_in        => TRUE
+  )
+  PORT MAP (
+    tx_serial_out => tx_serial_1,
+    rx_serial_in  => tx_serial_0
+  );
+  
+END tb;