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Commit 1df5cd49 authored by Shoshkov's avatar Shoshkov
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remove unused files

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applications/compaan/libraries/src/vhdl/compaan_design.vhd deleted 100644 → 0
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View file @ d9f09b95
------------------------------------------------------------------
-- TOP LEVEL
------------------------------------------------------------------
library IEEE, dp_lib;
use IEEE.STD_LOGIC_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
entity compaan_design is
generic (
BLOCKS_PER_SYNC : natural := 10
);
port (
--data_in_Data : in std_logic_vector(31 downto 0 );
--data_in_Control : in std_logic;
--data_in_Read : out std_logic;
--data_in_Exists : in std_logic;
--data_in_SOP : out std_logic;
--data_in_EOP : out std_logic;
--data_out_Data : out std_logic_vector(31 downto 0 );
--data_out_Control : out std_logic;
--data_out_Write : out std_logic;
--data_out_Full : in std_logic;
--data_out_SOP : out std_logic;
--data_out_EOP : out std_logic;
-- ST sink
snk_out : OUT t_dp_siso;
snk_in : IN t_dp_sosi;
-- ST source
src_in : IN t_dp_siso;
src_out : OUT t_dp_sosi;
TEST_STOP : out std_logic_vector(2 downto 0 );
TEST_ERROR : out std_logic_vector(2 downto 0 );
TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
address : in std_logic_vector(18 downto 0 );
read_data : out std_logic_vector(31 downto 0 );
read_en : in std_logic;
write_en : in std_logic;
write_data : in std_logic_vector(31 downto 0 );
KPN_CLK : in std_logic;
KPN_RST : in std_logic
);
end compaan_design;
architecture STRUCTURE of compaan_design is
signal data_in_Data : std_logic_vector(31 downto 0);
signal data_in_control : std_logic;
signal data_in_Read : std_logic;
signal data_in_Exists : std_logic;
signal data_in_SOP : std_logic;
signal data_in_EOP : std_logic;
signal data_out_Data_c : std_logic_vector(31 downto 0);
signal data_out_Control_c : std_logic;
signal data_out_Write_c : std_logic;
signal data_out_Data : std_logic_vector(31 downto 0);
signal data_out_Control : std_logic;
signal data_out_Write : std_logic;
signal data_out_Full : std_logic;
signal data_out_SOP : std_logic;
signal data_out_EOP : std_logic;
begin
-- wrapper -> ipcore
data_in_Data <= snk_in.data(31 downto 0);
snk_out.ready <= data_in_Read;
data_in_Exists <= snk_in.valid;
data_in_SOP <= snk_in.sop;
data_in_EOP <= snk_in.eop;
-- ipcore --> wrapper
data_out_Full <= not src_in.ready;
src_out.valid <= data_out_Write;
src_out.data(31 downto 0) <= data_out_Data;
src_out.sop <= data_out_SOP;
src_out.eop <= data_out_EOP;
-- Compaan ipcore
u_compaan_design : ENTITY work.ipcore
PORT MAP (
data_in_Data => data_in_Data,
data_in_Control => data_in_Control,
data_in_Read => data_in_Read,
data_in_Exists => data_in_Exists,
data_out_Data => data_out_Data_c,
data_out_Control => data_out_Control_c,
data_out_Write => data_out_Write_c,
data_out_Full => data_out_Full,
TEST_STOP => TEST_STOP,
TEST_ERROR => TEST_ERROR,
TEST_FIFO_FULL => TEST_FIFO_FULL,
TEST_BLOCK_RD => TEST_BLOCK_RD,
address => address,
read_data => read_data,
read_en => read_en,
write_en => write_en,
write_data => write_data,
KPN_CLK => KPN_CLK,
KPN_RST => KPN_RST
);
u_pkg_signals_gen : ENTITY work.pkg_signals
GENERIC MAP (
BLOCKS_PER_SYNC => BLOCKS_PER_SYNC
)
port map (
write_in => data_out_Write_c,
data_in => data_out_Data_c,
control_in => data_out_Control_c,
write_out => data_out_Write,
data_out => data_out_Data,
control_out => data_out_Control,
eop_out => data_out_EOP,
sop_out => data_out_SOP,
RST => KPN_RST,
CLK => KPN_CLK
);
end architecture STRUCTURE;
applications/compaan/libraries/src/vhdl/compaan_unb1_dp_offload.vhd deleted 100644 → 0
+ 0
− 586
View file @ d9f09b95
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