From 1df5cd49d1537c30d069c38298ee047c9a82996a Mon Sep 17 00:00:00 2001
From: Shoshkov <shoshkov>
Date: Mon, 8 Jun 2015 09:21:25 +0000
Subject: [PATCH] remove unused files
---
.../libraries/src/vhdl/compaan_design.vhd | 135 ----
.../src/vhdl/compaan_unb1_dp_offload.vhd | 586 ------------------
.../src/vhdl/mmm_compaan_unb1_dp_offload.vhd | 460 --------------
3 files changed, 1181 deletions(-)
delete mode 100644 applications/compaan/libraries/src/vhdl/compaan_design.vhd
delete mode 100644 applications/compaan/libraries/src/vhdl/compaan_unb1_dp_offload.vhd
delete mode 100644 applications/compaan/libraries/src/vhdl/mmm_compaan_unb1_dp_offload.vhd
diff --git a/applications/compaan/libraries/src/vhdl/compaan_design.vhd b/applications/compaan/libraries/src/vhdl/compaan_design.vhd
deleted file mode 100644
index f508da2082..0000000000
--- a/applications/compaan/libraries/src/vhdl/compaan_design.vhd
+++ /dev/null
@@ -1,135 +0,0 @@
-------------------------------------------------------------------
--- TOP LEVEL
-------------------------------------------------------------------
-library IEEE, dp_lib;
-use IEEE.STD_LOGIC_1164.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-
-entity compaan_design is
- generic (
- BLOCKS_PER_SYNC : natural := 10
- );
- port (
-
- --data_in_Data : in std_logic_vector(31 downto 0 );
- --data_in_Control : in std_logic;
- --data_in_Read : out std_logic;
- --data_in_Exists : in std_logic;
- --data_in_SOP : out std_logic;
- --data_in_EOP : out std_logic;
-
- --data_out_Data : out std_logic_vector(31 downto 0 );
- --data_out_Control : out std_logic;
- --data_out_Write : out std_logic;
- --data_out_Full : in std_logic;
- --data_out_SOP : out std_logic;
- --data_out_EOP : out std_logic;
-
- -- ST sink
- snk_out : OUT t_dp_siso;
- snk_in : IN t_dp_sosi;
-
- -- ST source
- src_in : IN t_dp_siso;
- src_out : OUT t_dp_sosi;
-
- TEST_STOP : out std_logic_vector(2 downto 0 );
- TEST_ERROR : out std_logic_vector(2 downto 0 );
- TEST_FIFO_FULL : out std_logic_vector(1 downto 0 );
- TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
- address : in std_logic_vector(18 downto 0 );
- read_data : out std_logic_vector(31 downto 0 );
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0 );
-
- KPN_CLK : in std_logic;
- KPN_RST : in std_logic
- );
-end compaan_design;
-
-architecture STRUCTURE of compaan_design is
-
-
- signal data_in_Data : std_logic_vector(31 downto 0);
- signal data_in_control : std_logic;
- signal data_in_Read : std_logic;
- signal data_in_Exists : std_logic;
- signal data_in_SOP : std_logic;
- signal data_in_EOP : std_logic;
-
- signal data_out_Data_c : std_logic_vector(31 downto 0);
- signal data_out_Control_c : std_logic;
- signal data_out_Write_c : std_logic;
-
- signal data_out_Data : std_logic_vector(31 downto 0);
- signal data_out_Control : std_logic;
- signal data_out_Write : std_logic;
- signal data_out_Full : std_logic;
- signal data_out_SOP : std_logic;
- signal data_out_EOP : std_logic;
-
-begin
-
- -- wrapper -> ipcore
- data_in_Data <= snk_in.data(31 downto 0);
- snk_out.ready <= data_in_Read;
- data_in_Exists <= snk_in.valid;
- data_in_SOP <= snk_in.sop;
- data_in_EOP <= snk_in.eop;
-
- -- ipcore --> wrapper
- data_out_Full <= not src_in.ready;
- src_out.valid <= data_out_Write;
- src_out.data(31 downto 0) <= data_out_Data;
- src_out.sop <= data_out_SOP;
- src_out.eop <= data_out_EOP;
-
- -- Compaan ipcore
- u_compaan_design : ENTITY work.ipcore
- PORT MAP (
-
- data_in_Data => data_in_Data,
- data_in_Control => data_in_Control,
- data_in_Read => data_in_Read,
- data_in_Exists => data_in_Exists,
-
- data_out_Data => data_out_Data_c,
- data_out_Control => data_out_Control_c,
- data_out_Write => data_out_Write_c,
- data_out_Full => data_out_Full,
-
- TEST_STOP => TEST_STOP,
- TEST_ERROR => TEST_ERROR,
- TEST_FIFO_FULL => TEST_FIFO_FULL,
- TEST_BLOCK_RD => TEST_BLOCK_RD,
- address => address,
- read_data => read_data,
- read_en => read_en,
- write_en => write_en,
- write_data => write_data,
-
- KPN_CLK => KPN_CLK,
- KPN_RST => KPN_RST
- );
-
- u_pkg_signals_gen : ENTITY work.pkg_signals
- GENERIC MAP (
- BLOCKS_PER_SYNC => BLOCKS_PER_SYNC
- )
- port map (
- write_in => data_out_Write_c,
- data_in => data_out_Data_c,
- control_in => data_out_Control_c,
-
- write_out => data_out_Write,
- data_out => data_out_Data,
- control_out => data_out_Control,
- eop_out => data_out_EOP,
- sop_out => data_out_SOP,
-
- RST => KPN_RST,
- CLK => KPN_CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/src/vhdl/compaan_unb1_dp_offload.vhd b/applications/compaan/libraries/src/vhdl/compaan_unb1_dp_offload.vhd
deleted file mode 100644
index 8c62647fd9..0000000000
--- a/applications/compaan/libraries/src/vhdl/compaan_unb1_dp_offload.vhd
+++ /dev/null
@@ -1,586 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2013
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose:
--- . Test dp_offload_tx and dp_offload_rx components
--- Description:
--- . Block generators generate data blocks that flow from dp_offload_tx to dp_offload_rx
--- instances via 1GbE (32b user interface)
-
-LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, diag_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_str_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE unb1_board_lib.unb1_board_pkg.ALL;
-USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE tech_tse_lib.tech_tse_pkg.ALL;
-USE eth_lib.eth_pkg.ALL;
-USE common_lib.common_network_layers_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
-
-ENTITY compaan_unb1_dp_offload IS
- GENERIC (
- g_sim : BOOLEAN := FALSE; -- set by ModelSim
- g_sim_unb_nr : NATURAL := 0; -- set by ModelSim
- g_sim_node_nr : NATURAL := 0; -- set by ModelSim
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
- );
- PORT (
- -- GENERAL
--- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
- PPS : IN STD_LOGIC;
- WDI : OUT STD_LOGIC;
- INTA : INOUT STD_LOGIC;
- INTB : INOUT STD_LOGIC;
-
- -- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-
- -- I2C Interface to Sensors
- sens_sc : INOUT STD_LOGIC;
- sens_sd : INOUT STD_LOGIC;
-
- -- 1GbE Control Interface
- ETH_clk : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC;
- ETH_SGOUT : OUT STD_LOGIC
- );
-END compaan_unb1_dp_offload;
-
-
-ARCHITECTURE str OF compaan_unb1_dp_offload IS
-
- CONSTANT c_design_name : STRING := "compaan_unb1_dp_offload";
-
- CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_tech_tse_data_w, c_xgmii_data_w
-
- -- Revision controlled constants
- CONSTANT c_use_1GbE : BOOLEAN := TRUE;
- CONSTANT c_nof_streams : NATURAL := 3;
-
- CONSTANT c_data_w : NATURAL := c_tech_tse_data_w;
-
- -- Block generator
- CONSTANT c_bg_block_size : NATURAL := 900;
- CONSTANT c_bg_gapsize : NATURAL := 100;
- CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
- -- dp_offload_tx
- CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
- CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
-
- CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
-
- CONSTANT c_use_jumbo_frames : BOOLEAN := TRUE;
- CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
-
- CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
- CONSTANT c_max_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
- CONSTANT c_nof_header_words : NATURAL := field_slv_len(c_hdr_field_arr) / c_data_w;
- CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
- CONSTANT c_nof_crc_words : NATURAL := 1;
- CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
- CONSTANT c_max_udp_payload_nof_words : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
- CONSTANT c_max_nof_words_per_block : NATURAL := c_bg_block_size;
- CONSTANT c_min_nof_words_per_block : NATURAL := 1;
- CONSTANT c_def_nof_words_per_block : NATURAL := sel_a_b(c_use_1GbE, c_def_1GbE_block_size, c_bg_block_size);
- CONSTANT c_max_nof_blocks_per_packet : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
- CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
-
- SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
-
- -- System
- SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_clk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
- SIGNAL dp_rst : STD_LOGIC;
- SIGNAL dp_clk : STD_LOGIC;
- -- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
-
- SIGNAL eth1g_tse_clk : STD_LOGIC;
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi;
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi;
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC;
- SIGNAL eth1g_ram_mosi : t_mem_mosi;
- SIGNAL eth1g_ram_miso : t_mem_miso;
-
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
-
- SIGNAL reg_diag_bg_mosi : t_mem_mosi;
- SIGNAL reg_diag_bg_miso : t_mem_miso;
- SIGNAL ram_diag_bg_mosi : t_mem_mosi;
- SIGNAL ram_diag_bg_miso : t_mem_miso;
-
- SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
- SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-
- SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
- SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
- SIGNAL ram_diag_data_buf_miso : t_mem_miso;
- SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
- SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-
- SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
-
- SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
-
- SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
-
- SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
-
- SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
-
- -- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
-
-BEGIN
-
- -----------------------------------------------------------------------------
- -- TX: Block generator
- -----------------------------------------------------------------------------
- u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
- GENERIC MAP (
- g_nof_output_streams => c_nof_streams,
- g_buf_dat_w => c_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso
- );
-
- -----------------------------------------------------------------------------
- -- TX: dp_offload_tx
- -----------------------------------------------------------------------------
- u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
- GENERIC MAP (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_use_complex => FALSE,
- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_def_nof_words_per_block => c_def_nof_words_per_block,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
- g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_output_fifo_depth => c_max_frame_nof_words,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_ovr_init => c_hdr_field_ovr_init
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_mosi => reg_dp_offload_tx_mosi,
- reg_miso => reg_dp_offload_tx_miso,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- reg_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
-
- snk_in_arr => block_gen_src_out_arr,
- snk_out_arr => block_gen_src_in_arr,
-
- src_out_arr => dp_offload_tx_src_out_arr,
- src_in_arr => dp_offload_tx_src_in_arr,
-
- hdr_fields_in_arr => hdr_fields_in_arr
- );
-
- gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
- -- dst = src
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
-
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr")) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
-
- -- dst port goes through 4000,4001,4002
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port") DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
-
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Interface : Loopback
- -----------------------------------------------------------------------------
- gen_loopback : IF c_use_1GbE=FALSE GENERATE
- dp_offload_rx_snk_in_arr <= dp_offload_tx_src_out_arr;
- dp_offload_tx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Interface : 1GbE
- -----------------------------------------------------------------------------
- gen_wires_1GbE : IF c_use_1GbE=TRUE GENERATE
- eth1g_udp_tx_sosi_arr <= dp_offload_tx_src_out_arr;
- dp_offload_tx_src_in_arr <= eth1g_udp_tx_siso_arr;
-
- dp_offload_rx_snk_in_arr <= eth1g_udp_rx_sosi_arr;
- eth1g_udp_rx_siso_arr <= dp_offload_rx_snk_out_arr;
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- RX: dp_offload_rx
- -----------------------------------------------------------------------------
- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
- GENERIC MAP (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => c_use_1GbE,
- g_crc_nof_words => c_nof_crc_words
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr
- );
-
- gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
- diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
- diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- RX: Data buffers and BSN monitors
- -----------------------------------------------------------------------------
- dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr;
-
- gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams-1 GENERATE
- diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
- diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
- diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
- diag_data_buf_snk_in_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
- diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
- END GENERATE;
-
- u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
- GENERIC MAP (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => TRUE,
- g_sync_timeout => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
- g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
- g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync*c_bg_block_size+1),
- g_log_first_bsn => TRUE
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
-
- diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
-
- u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
- GENERIC MAP (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => TRUE
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sop,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
-
- -----------------------------------------------------------------------------
- -- General control function
- -----------------------------------------------------------------------------
- u_ctrl_unb1_board : ENTITY unb1_board_lib.ctrl_unb1_board
- GENERIC MAP (
- g_sim => g_sim,
- g_design_name => c_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams,
- g_dp_clk_use_pll => FALSE
- )
- PORT MAP (
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => OPEN,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- UniBoard FPGA pins
- CLK => '0',
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
-
- -----------------------------------------------------------------------------
- -- MM master
- -----------------------------------------------------------------------------
- u_mmm_compaan_unb1_dp_offload : ENTITY work.mmm_compaan_unb1_dp_offload
- GENERIC MAP (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr
- )
- PORT MAP(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- dp_clk => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
-
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
-
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso
- );
-
-END str;
diff --git a/applications/compaan/libraries/src/vhdl/mmm_compaan_unb1_dp_offload.vhd b/applications/compaan/libraries/src/vhdl/mmm_compaan_unb1_dp_offload.vhd
deleted file mode 100644
index 6050062cf9..0000000000
--- a/applications/compaan/libraries/src/vhdl/mmm_compaan_unb1_dp_offload.vhd
+++ /dev/null
@@ -1,460 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2013
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose:
--- . MM master for all MM peripherals in the compaan_unb1_dp_offload design
--- Description:
--- . Synthesis: a NIOS II (running app unb_osy) -based SOPC is instantiated:
--- . Cloks are generated by the PLL in the SOPC
--- . Access to MM buses via 1GbE and unb_osy application
--- . Application unb_osy initializes the 1GbE module
--- . Python controls/monitors MM peripherals by sending/receiving packets
--- . Simulation: an mm_file instance in instantiated for each MM bus:
--- . Clocks are generated by non-synthesizable VHDL
--- . Access to MM buses via file I/O
--- . Python controls/monitors MM peripherals by writing/reading files
--- . Additional sim.ctrl and sim.stat files are used for non-functional
--- Python<->ModelSim interaction such as getting the simulation time.
--- . g_sim_unb_nr and g_sim_node_nr are passed to the MM file instances so
--- Python can target the files using the same board + node arguments as
--- used to target hardware (--unb # --fn # --bn #)
-
-LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, tech_tse_lib, technology_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE common_lib.tb_common_mem_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
-USE unb1_board_lib.unb1_board_pkg.ALL;
-USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-USE mm_lib.mm_file_pkg.ALL;
-USE mm_lib.mm_file_unb_pkg.ALL;
-USE tech_tse_lib.tech_tse_pkg.ALL;
-USE tech_tse_lib.tb_tech_tse_pkg.ALL;
-USE eth_lib.eth_pkg.ALL;
-USE common_lib.common_network_layers_pkg.ALL;
-
-ENTITY mmm_compaan_unb1_dp_offload IS
- GENERIC (
- g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
- g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_nof_streams : NATURAL;
- g_bg_block_size : NATURAL;
- g_hdr_field_arr : t_common_field_arr
- );
- PORT (
- xo_clk : IN STD_LOGIC;
- xo_rst_n : IN STD_LOGIC;
- xo_rst : IN STD_LOGIC;
-
- mm_rst : IN STD_LOGIC;
- mm_clk : OUT STD_LOGIC;
- mm_locked : OUT STD_LOGIC;
-
- dp_clk : OUT STD_LOGIC;
-
- pout_wdi : OUT STD_LOGIC;
-
- -- Manual WDI override
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso;
-
- -- system_info
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso;
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi : OUT t_mem_mosi;
- reg_unb_sens_miso : IN t_mem_miso;
-
- -- eth1g
- eth1g_tse_clk : OUT STD_LOGIC;
- eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
- eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
-
- reg_dp_offload_tx_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_miso : IN t_mem_miso;
-
- reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
-
- reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
-
- reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
- reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
-
- reg_bsn_monitor_mosi : OUT t_mem_mosi;
- reg_bsn_monitor_miso : IN t_mem_miso;
-
- ram_diag_data_buf_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_miso : IN t_mem_miso;
-
- reg_diag_data_buf_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_miso : IN t_mem_miso;
-
- ram_diag_bg_mosi : OUT t_mem_mosi;
- ram_diag_bg_miso : IN t_mem_miso;
- reg_diag_bg_mosi : OUT t_mem_mosi;
- reg_diag_bg_miso : IN t_mem_miso
- );
-END mmm_compaan_unb1_dp_offload;
-
-ARCHITECTURE str OF mmm_compaan_unb1_dp_offload IS
-
- -- Clocks
- SIGNAL i_mm_clk : STD_LOGIC := '1';
- SIGNAL i_tse_clk : STD_LOGIC := '1';
- SIGNAL i_dp_clk : STD_LOGIC := '1';
- SIGNAL i_cal_rec_clk : STD_LOGIC := '1';
-
- -- Block generator
- CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(g_nof_streams* pow2(ceil_log2(g_bg_block_size)));
-
- -- dp_offload
- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
- CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_adr_w));
-
- CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
- CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
- CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
-
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := g_hdr_field_arr'LENGTH;
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
-
- CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
- CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
- CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
-
- -- BSN monitors
- CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-
- -- Simulation
- CONSTANT c_mm_clk_period : TIME := 8 ns;
- CONSTANT c_tech_tse_clk_period : TIME := 8 ns;
- CONSTANT c_dp_clk_period : TIME := 5 ns;
-
- CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
- CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
-
- CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
-
- SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
- SIGNAL sim_eth_psc_access : STD_LOGIC;
-
- SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_reg_miso : t_mem_miso;
-
- SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
-
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_mm_clk_period : TIME := c_mm_clk_period;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-BEGIN
-
- mm_clk <= i_mm_clk;
- eth1g_tse_clk <= i_tse_clk;
- dp_clk <= i_dp_clk;
-
- ----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
- ----------------------------------------------------------------------------
- gen_mm_file_io : IF g_sim = TRUE GENERATE
-
- i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;
- i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
- i_tse_clk <= NOT i_tse_clk AFTER c_tech_tse_clk_period/2;
-
- mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
- eth1g_mm_rst <= '1', '0' AFTER c_tech_tse_clk_period*5;
-
- u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
-
- u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
-
- u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
-
- u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
-
- u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
-
- u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
-
- u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
-
- u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
-
- u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
-
- u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
-
- u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
-
- u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
-
- u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
-
- u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
-
- ----------------------------------------------------------------------------
- -- 1GbE setup sequence normally performed by unb_os@NIOS
- ----------------------------------------------------------------------------
- p_eth_setup : PROCESS
- BEGIN
- sim_eth_mm_bus_switch <= '1';
-
- eth1g_tse_mosi.wr <= '0';
- eth1g_tse_mosi.rd <= '0';
- WAIT FOR 400 ns;
- WAIT UNTIL rising_edge(i_mm_clk);
- proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
- -- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
- sim_eth_mm_bus_switch <= '0';
-
- WAIT;
- END PROCESS;
-
- p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
- BEGIN
- IF sim_eth_mm_bus_switch = '1' THEN
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- ELSE
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- END IF;
- END PROCESS;
-
- ----------------------------------------------------------------------------
- -- Procedure that polls a sim control file that can be used to e.g. get
- -- the simulation time in ns
- ----------------------------------------------------------------------------
- mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
- END GENERATE;
-
- ----------------------------------------------------------------------------
- -- SOPC for synthesis
- ----------------------------------------------------------------------------
- gen_sopc : IF g_sim = FALSE GENERATE
- u_sopc : ENTITY work.sopc_compaan_unb1_dp_offload
- PORT MAP (
- clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- 125 MHz system clock
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
- dp_clk => i_dp_clk,
- cal_reconf_clk => OPEN,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w-1 DOWNTO 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w-1 DOWNTO 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx
- coe_address_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_hdr_ovr
- coe_address_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_rx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0)
- );
- END GENERATE;
-
-END str;
--
GitLab