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applications/compaan/designs/compaan_unb1_10g_passthru/src/vhdl/compaan_design.vhd

@@ -56,7 +56,7 @@ architecture STRUCTURE of compaan_design is
 begin 
 	
 	snk_out.xon   <= '1';				   
-	snk_out.ready <= '1'; -- data_in_Read; 
+	snk_out.ready <= data_in_Read; 
 	
   -- wrapper -> ipcore     		
 	data_in_Data <= snk_in.data(31 downto 0);      

applications/compaan/libraries/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd

@@ -56,6 +56,7 @@ architecture RTL of read_mux is
   signal sl_read  : std_logic;
   signal sl_exist : std_logic;
   signal TMP      : std_logic_vector(PORT_WIDTH-1 downto 0);
+  signal TMP_in   : std_logic_vector(PORT_WIDTH-1 downto 0);
 begin
   EXIST   <= READ_EN and sl_exist;
   sl_read <= READ_EN and READ;
@@ -70,7 +71,16 @@ begin
     READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
   end generate;
   
+  p_regs : PROCESS(CLK)
+  BEGIN 
+    IF RISING_EDGE(CLK) THEN 
+      TMP <= TMP_in; 
+    END IF; 
+  END PROCESS;      
+   
+   
   MUX_DATA :  process(CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
+    VARIABLE v_TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
   begin
     OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
     for i in 0 to N_PORTS-1 loop
@@ -78,14 +88,10 @@ begin
       
         if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
           OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);     
-					TMP <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);     -- keep a copy of the value
-	        end if ;
-	        
-			  if( OBTAIN(i) = '0' and RELEASE(i) = '0') then
-					OUT_PORT <= TMP;        
+          v_TMP := IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);     -- keep a copy of the value
         end if;
         
-			  if( OBTAIN(i) = '0' and RELEASE(i) = '1') then
+        if( OBTAIN(i) = '0') then
           OUT_PORT <= TMP;        
         end if; 
         
@@ -97,9 +103,11 @@ begin
         end if;
       end if;        
     end loop;
+    TMP_in <= v_TMP;
   end process;
   
-   MUX_EXIST :  process(EXISTS, READ, CONTROL)
+  
+  MUX_EXIST :  process(EXISTS, CONTROL)
   begin
     sl_exist <= '0';
     for i in 0 to N_PORTS-1 loop

applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_1/src/vhdl/passthru2rtl_hwn_nd_1.vhd

@@ -273,10 +273,10 @@ architecture RTL of passthru2rtl_hwn_nd_1 is
    signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
    -- 
    -- 
-   signal sl_halt             : std_logic := '0';
+   signal sl_halt             : std_logic;
    signal sl_halted           : std_logic;
-   signal sl_halt_wr          : std_logic := '0';
-   signal sl_halt_rd          : std_logic := '0';
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
    signal sl_param_halt_wr    : std_logic;
    signal sl_param_halt_rd    : std_logic;
    signal sl_done_wr          : std_logic;
@@ -451,6 +451,9 @@ begin
    -- ==========================================================
    -- =       PARAMETERIZATION                                 =
    -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
 --   sl_halted  <= sl_sof_rd;
    STOP <= sl_done_wr;
    ERROR <= sl_error;

applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_2/src/vhdl/passthru2rtl_hwn_nd_2.vhd

@@ -273,10 +273,10 @@ architecture RTL of passthru2rtl_hwn_nd_2 is
    signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
    -- 
    -- 
-   signal sl_halt             : std_logic := '0';
+   signal sl_halt             : std_logic;
    signal sl_halted           : std_logic;
-   signal sl_halt_wr          : std_logic := '0';
-   signal sl_halt_rd          : std_logic := '0';
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
    signal sl_param_halt_wr    : std_logic;
    signal sl_param_halt_rd    : std_logic;
    signal sl_done_wr          : std_logic;
@@ -451,6 +451,9 @@ begin
    -- ==========================================================
    -- =       PARAMETERIZATION                                 =
    -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
 --   sl_halted  <= sl_sof_rd;
    STOP <= sl_done_wr;
    ERROR <= sl_error;

applications/compaan/libraries/passthru/src/vhdl/passthru.vhd

@@ -229,13 +229,6 @@ begin
 -- Instanciate the wrappers (HWN and Edges)
 
 
---test--
-
-
-  -- I_image_pci_in_Read <= '1';
-  -- I_image_pci_out_Data <= I_image_pci_in_Data;
-  -- I_image_pci_out_Write <= I_image_pci_in_Exists AND (NOT I_image_pci_out_Full);
-
   passthru2rtl_hwn_nd_1_ip : passthru2rtl_hwn_nd_1_ip_wrapper
 	port map (
 		image_pci_in_Rd => I_image_pci_in_Read,
@@ -246,9 +239,9 @@ begin
 		ND_1OP_1_Wr => signal_ed_1_out_FSL_M_Write,
 		ND_1OP_1_Dout(31 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 31),
 		ND_1OP_1_Full => signal_ed_1_out_FSL_M_Full,
-		PARAM_DT => signal_PARAM_DT,
 		ND_1OP_1_CLK => open,
 		ND_1OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
 		PARAM_LD => signal_PARAM_LD,
 		STOP => signal_hwn_nd_1_STOP,
 		ERROR => signal_hwn_nd_1_ERROR,