From 1d4fb7f12f212d383e49f28156668f134582eeed Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Sat, 3 Jun 2017 11:02:50 +0000
Subject: [PATCH]
---
.../src/vhdl/compaan_design.vhd | 2 +-
.../common/hwnode/src/vhdl/read_mux.vhd | 184 +++++++++---------
.../src/vhdl/passthru2rtl_hwn_nd_1.vhd | 9 +-
.../src/vhdl/passthru2rtl_hwn_nd_2.vhd | 9 +-
.../libraries/passthru/src/vhdl/passthru.vhd | 9 +-
5 files changed, 110 insertions(+), 103 deletions(-)
diff --git a/applications/compaan/designs/compaan_unb1_10g_passthru/src/vhdl/compaan_design.vhd b/applications/compaan/designs/compaan_unb1_10g_passthru/src/vhdl/compaan_design.vhd
index 809f8f45a6..771ecdb5a7 100644
--- a/applications/compaan/designs/compaan_unb1_10g_passthru/src/vhdl/compaan_design.vhd
+++ b/applications/compaan/designs/compaan_unb1_10g_passthru/src/vhdl/compaan_design.vhd
@@ -56,7 +56,7 @@ architecture STRUCTURE of compaan_design is
begin
snk_out.xon <= '1';
- snk_out.ready <= '1'; -- data_in_Read;
+ snk_out.ready <= data_in_Read;
-- wrapper -> ipcore
data_in_Data <= snk_in.data(31 downto 0);
diff --git a/applications/compaan/libraries/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd b/applications/compaan/libraries/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
index 72c89bfb71..41bd6188aa 100644
--- a/applications/compaan/libraries/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
+++ b/applications/compaan/libraries/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
@@ -27,102 +27,110 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity read_mux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
+ generic(
+ N_PORTS : natural := 1;
+ PORT_WIDTH : natural := 32
+ );
+ port(
+ IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+ EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
+ READS : out std_logic_vector(N_PORTS-1 downto 0);
+ SOFS : in std_logic_vector(N_PORTS-1 downto 0);
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CLK : in std_logic;
+ OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
+ EXIST : out std_logic;
+ READ : in std_logic;
+ SOF : in std_logic;
+
+ READ_EN : in std_logic;
+ READ_ST : out std_logic;
+ CLK : in std_logic;
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
+ RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
+ OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
+ CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
+ );
end read_mux;
architecture RTL of read_mux is
- signal sl_read : std_logic;
- signal sl_exist : std_logic;
- signal TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
+ signal sl_read : std_logic;
+ signal sl_exist : std_logic;
+ signal TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
+ signal TMP_in : std_logic_vector(PORT_WIDTH-1 downto 0);
begin
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= sl_read and sl_exist;
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- --
- -- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read and (not SOFS(i) or SOF);
- -- The Reorder work showed problems as a result of SOFS signal. For now switched off until
- -- its use becomes clear again. BK 31mar14
- --
- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
- end generate;
-
- MUX_DATA : process(CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
- begin
- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1') then
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- TMP <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH); -- keep a copy of the value
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '0') then
- OUT_PORT <= TMP;
- end if ;
+ EXIST <= READ_EN and sl_exist;
+ sl_read <= READ_EN and READ;
+ READ_ST <= sl_read and sl_exist;
- if( OBTAIN(i) = '0' and RELEASE(i) = '1') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '1') then
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity WARNING;
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- end if ;
- end if;
- end loop;
- end process;
-
- MUX_EXIST : process(EXISTS, READ, CONTROL)
- begin
- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- sl_exist <= EXISTS(i);
- end if;
- end loop;
- end process;
+ DEMUX_GEN : for i in 0 to N_PORTS-1 generate
+ --
+ -- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read and (not SOFS(i) or SOF);
+ -- The Reorder work showed problems as a result of SOFS signal. For now switched off until
+ -- its use becomes clear again. BK 31mar14
+ --
+ READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
+ end generate;
+
+ p_regs : PROCESS(CLK)
+ BEGIN
+ IF RISING_EDGE(CLK) THEN
+ TMP <= TMP_in;
+ END IF;
+ END PROCESS;
- -- Checks. For simulation only
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
+ MUX_DATA : process(CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
+ VARIABLE v_TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
+ begin
+ OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
+ for i in 0 to N_PORTS-1 loop
+ if( CONTROL(i) = '1') then
+
+ if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
+ OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+ v_TMP := IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH); -- keep a copy of the value
+ end if;
+
+ if( OBTAIN(i) = '0') then
+ OUT_PORT <= TMP;
+ end if;
+
+ if( OBTAIN(i) = '1' and RELEASE(i) = '1') then
+ --assert false
+ -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
+ -- severity WARNING;
+ OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
+ end if;
+ end if;
+ end loop;
+ TMP_in <= v_TMP;
+ end process;
+
+
+ MUX_EXIST : process(EXISTS, CONTROL)
+ begin
+ sl_exist <= '0';
+ for i in 0 to N_PORTS-1 loop
+ if( CONTROL(i) = '1' ) then
+ sl_exist <= EXISTS(i);
+ end if;
+ end loop;
+ end process;
+
+
+ -- Checks. For simulation only
+ process(CONTROL)
+ variable c : integer;
+ begin
+ c := 0;
+ for i in 0 to CONTROL'Length-1 loop
+ if (CONTROL(i)='1') then
+ c := c + 1;
+ end if;
+ end loop;
+ assert (c <= 1)
+ report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
+ severity ERROR;
+ end process;
end RTL;
diff --git a/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_1/src/vhdl/passthru2rtl_hwn_nd_1.vhd b/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_1/src/vhdl/passthru2rtl_hwn_nd_1.vhd
index 7132282c95..aff20a1e7a 100644
--- a/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_1/src/vhdl/passthru2rtl_hwn_nd_1.vhd
+++ b/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_1/src/vhdl/passthru2rtl_hwn_nd_1.vhd
@@ -273,10 +273,10 @@ architecture RTL of passthru2rtl_hwn_nd_1 is
signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
--
--
- signal sl_halt : std_logic := '0';
+ signal sl_halt : std_logic;
signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic := '0';
- signal sl_halt_rd : std_logic := '0';
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
signal sl_param_halt_wr : std_logic;
signal sl_param_halt_rd : std_logic;
signal sl_done_wr : std_logic;
@@ -451,6 +451,9 @@ begin
-- ==========================================================
-- = PARAMETERIZATION =
-- ==========================================================
+ -- no parameters
+ sl_halt_rd <= '0';
+ sl_halt_wr <= '0';
-- sl_halted <= sl_sof_rd;
STOP <= sl_done_wr;
ERROR <= sl_error;
diff --git a/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_2/src/vhdl/passthru2rtl_hwn_nd_2.vhd b/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_2/src/vhdl/passthru2rtl_hwn_nd_2.vhd
index 713794558c..898a0a0899 100644
--- a/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_2/src/vhdl/passthru2rtl_hwn_nd_2.vhd
+++ b/applications/compaan/libraries/passthru/compaandesign_com/passthru2rtl/hwn_nd_2/src/vhdl/passthru2rtl_hwn_nd_2.vhd
@@ -273,10 +273,10 @@ architecture RTL of passthru2rtl_hwn_nd_2 is
signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
--
--
- signal sl_halt : std_logic := '0';
+ signal sl_halt : std_logic;
signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic := '0';
- signal sl_halt_rd : std_logic := '0';
+ signal sl_halt_wr : std_logic;
+ signal sl_halt_rd : std_logic;
signal sl_param_halt_wr : std_logic;
signal sl_param_halt_rd : std_logic;
signal sl_done_wr : std_logic;
@@ -451,6 +451,9 @@ begin
-- ==========================================================
-- = PARAMETERIZATION =
-- ==========================================================
+ -- no parameters
+ sl_halt_rd <= '0';
+ sl_halt_wr <= '0';
-- sl_halted <= sl_sof_rd;
STOP <= sl_done_wr;
ERROR <= sl_error;
diff --git a/applications/compaan/libraries/passthru/src/vhdl/passthru.vhd b/applications/compaan/libraries/passthru/src/vhdl/passthru.vhd
index 6aeb596738..f75f22c2bc 100644
--- a/applications/compaan/libraries/passthru/src/vhdl/passthru.vhd
+++ b/applications/compaan/libraries/passthru/src/vhdl/passthru.vhd
@@ -229,13 +229,6 @@ begin
-- Instanciate the wrappers (HWN and Edges)
---test--
-
-
- -- I_image_pci_in_Read <= '1';
- -- I_image_pci_out_Data <= I_image_pci_in_Data;
- -- I_image_pci_out_Write <= I_image_pci_in_Exists AND (NOT I_image_pci_out_Full);
-
passthru2rtl_hwn_nd_1_ip : passthru2rtl_hwn_nd_1_ip_wrapper
port map (
image_pci_in_Rd => I_image_pci_in_Read,
@@ -246,9 +239,9 @@ begin
ND_1OP_1_Wr => signal_ed_1_out_FSL_M_Write,
ND_1OP_1_Dout(31 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 31),
ND_1OP_1_Full => signal_ed_1_out_FSL_M_Full,
- PARAM_DT => signal_PARAM_DT,
ND_1OP_1_CLK => open,
ND_1OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
+ PARAM_DT => signal_PARAM_DT,
PARAM_LD => signal_PARAM_LD,
STOP => signal_hwn_nd_1_STOP,
ERROR => signal_hwn_nd_1_ERROR,
--
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