fixed tb_mms_dp_gain_serial_arr.vhd

libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd

@@ -57,7 +57,7 @@ ARCHITECTURE tb OF tb_mms_dp_gain_serial_arr IS
   CONSTANT c_mm_clk_period              : TIME := 20 ns;
   CONSTANT c_dp_clk_period              : TIME := 10 ns;
   CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
-  CONSTANT c_dut_latency                : NATURAL := 5;    -- = 3 for the real or complex multiplier + 2 for the RAM read latency
+  CONSTANT c_dut_latency                : NATURAL := 4;    -- = 3 for the real or complex multiplier + 1 for the RAM read latency
   
   CONSTANT c_real_multiply              : BOOLEAN := g_complex_data=FALSE AND g_complex_gain=FALSE;
   CONSTANT c_nof_gains_w                : NATURAL := ceil_log2(g_nof_gains);