From 1c16ff219f74e89e410f3ce2e99531a8850f4662 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Tue, 9 Aug 2022 08:38:31 +0200 Subject: [PATCH] fixed tb_mms_dp_gain_serial_arr.vhd --- libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd index 43da667fd7..23bc0cbdaa 100644 --- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd +++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd @@ -57,7 +57,7 @@ ARCHITECTURE tb OF tb_mms_dp_gain_serial_arr IS CONSTANT c_mm_clk_period : TIME := 20 ns; CONSTANT c_dp_clk_period : TIME := 10 ns; CONSTANT c_cross_clock_domain_latency : NATURAL := 20; - CONSTANT c_dut_latency : NATURAL := 5; -- = 3 for the real or complex multiplier + 2 for the RAM read latency + CONSTANT c_dut_latency : NATURAL := 4; -- = 3 for the real or complex multiplier + 1 for the RAM read latency CONSTANT c_real_multiply : BOOLEAN := g_complex_data=FALSE AND g_complex_gain=FALSE; CONSTANT c_nof_gains_w : NATURAL := ceil_log2(g_nof_gains); -- GitLab