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Commit 0a6099d7 authored by Eric Kooistra's avatar Eric Kooistra
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Added tb_end. Corrected use of sync at sop and then delayed data to have sync before sop.

parent 7705d809
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...@@ -35,6 +35,9 @@ USE dp_lib.tb_dp_pkg.ALL; ...@@ -35,6 +35,9 @@ USE dp_lib.tb_dp_pkg.ALL;
-- > run 1 us -- > run 1 us
-- observe in_sosi, sum and sum_sync in wave window -- observe in_sosi, sum and sum_sync in wave window
-- expected sum after sum_sync are: 0, 120, 376, ... -- expected sum after sum_sync are: 0, 120, 376, ...
-- . sum([ 0:15]) = 120
-- . sum([16:31]) = 376
-- . sum([32:47]) = 632
ENTITY tb_aduh_mean_sum IS ENTITY tb_aduh_mean_sum IS
...@@ -64,6 +67,7 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS ...@@ -64,6 +67,7 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS
CONSTANT c_nof_accumulations : NATURAL := c_nof_symbols_per_sync; -- integration time in symbols CONSTANT c_nof_accumulations : NATURAL := c_nof_symbols_per_sync; -- integration time in symbols
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC; SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1'; SIGNAL clk : STD_LOGIC := '1';
...@@ -71,6 +75,7 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS ...@@ -71,6 +75,7 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS
SIGNAL st_en : STD_LOGIC := '1'; SIGNAL st_en : STD_LOGIC := '1';
SIGNAL st_sosi : t_dp_sosi := c_dp_sosi_rst; SIGNAL st_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL st_sosi_dly : t_dp_sosi := c_dp_sosi_rst;
SIGNAL st_siso : t_dp_siso := c_dp_siso_rdy; SIGNAL st_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL bsn : NATURAL; SIGNAL bsn : NATURAL;
...@@ -83,7 +88,7 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS ...@@ -83,7 +88,7 @@ ARCHITECTURE tb OF tb_aduh_mean_sum IS
BEGIN BEGIN
clk <= NOT clk AFTER clk_period/2; clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*5; rst <= '1', '0' AFTER clk_period*5;
-- ST domain -- ST domain
...@@ -101,29 +106,33 @@ BEGIN ...@@ -101,29 +106,33 @@ BEGIN
proc_common_wait_some_cycles(clk, 5); proc_common_wait_some_cycles(clk, 5);
-- Run some sync intervals with DSP counter data for the data field -- Run some sync intervals with DSP counter data for the data field
st_sosi.sync <= '1'; -- first sync
WAIT UNTIL rising_edge(clk);
FOR I IN 0 TO c_nof_sync-1 LOOP FOR I IN 0 TO c_nof_sync-1 LOOP
FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference -- Generate st_sosi with sync at sop
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_symbol := v_symbol + c_nof_symbols_per_block;
FOR J IN 0 TO c_nof_block_per_sync-2 LOOP
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
v_symbol := v_symbol + c_nof_symbols_per_block; v_symbol := v_symbol + c_nof_symbols_per_block;
END LOOP; END LOOP;
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_symbol := v_symbol + c_nof_symbols_per_block;
END LOOP; END LOOP;
st_sosi <= c_dp_sosi_rst; st_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(clk, 15);
tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
st_sosi_dly <= st_sosi WHEN rising_edge(clk);
-- Time stimuli -- Time stimuli
bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.sync='1'; bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.sync='1';
-- Add BSN to the ST data -- Add BSN to the ST data
p_in_sosi : PROCESS(st_sosi, bsn) p_in_sosi : PROCESS(st_sosi, st_sosi_dly, bsn)
BEGIN BEGIN
in_sosi <= st_sosi; in_sosi <= st_sosi_dly; -- data
in_sosi.bsn <= TO_DP_BSN(bsn); in_sosi.bsn <= TO_DP_BSN(bsn); -- bsn at sop
in_sosi.sync <= st_sosi.sync; -- sync before sop
END PROCESS; END PROCESS;
u_dut : ENTITY work.aduh_mean_sum u_dut : ENTITY work.aduh_mean_sum
......
...@@ -35,6 +35,9 @@ USE dp_lib.tb_dp_pkg.ALL; ...@@ -35,6 +35,9 @@ USE dp_lib.tb_dp_pkg.ALL;
-- > run 1 us -- > run 1 us
-- observe in_sosi, pwr_sum and pwr_sum_sync in wave window -- observe in_sosi, pwr_sum and pwr_sum_sync in wave window
-- expected pwr_sum after pwr_sync are: 0, 1240, 9176, ... -- expected pwr_sum after pwr_sync are: 0, 1240, 9176, ...
-- . sum([ 0:15].^2) = 1240
-- . sum([16:31].^2) = 9176
-- . sum([32:47].^2) = 25304
ENTITY tb_aduh_power_sum IS ENTITY tb_aduh_power_sum IS
GENERIC ( GENERIC (
...@@ -63,6 +66,7 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS ...@@ -63,6 +66,7 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS
CONSTANT c_nof_accumulations : NATURAL := c_nof_symbols_per_sync; -- integration time in symbols CONSTANT c_nof_accumulations : NATURAL := c_nof_symbols_per_sync; -- integration time in symbols
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC; SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1'; SIGNAL clk : STD_LOGIC := '1';
...@@ -70,6 +74,7 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS ...@@ -70,6 +74,7 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS
SIGNAL st_en : STD_LOGIC := '1'; SIGNAL st_en : STD_LOGIC := '1';
SIGNAL st_sosi : t_dp_sosi := c_dp_sosi_rst; SIGNAL st_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL st_sosi_dly : t_dp_sosi := c_dp_sosi_rst;
SIGNAL st_siso : t_dp_siso := c_dp_siso_rdy; SIGNAL st_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL bsn : NATURAL; SIGNAL bsn : NATURAL;
...@@ -82,7 +87,7 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS ...@@ -82,7 +87,7 @@ ARCHITECTURE tb OF tb_aduh_power_sum IS
BEGIN BEGIN
clk <= NOT clk AFTER clk_period/2; clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*5; rst <= '1', '0' AFTER clk_period*5;
-- ST domain -- ST domain
...@@ -100,29 +105,34 @@ BEGIN ...@@ -100,29 +105,34 @@ BEGIN
proc_common_wait_some_cycles(clk, 5); proc_common_wait_some_cycles(clk, 5);
-- Run some sync intervals with DSP counter data for the data field -- Run some sync intervals with DSP counter data for the data field
st_sosi.sync <= '1'; -- first sync
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
FOR I IN 0 TO c_nof_sync-1 LOOP FOR I IN 0 TO c_nof_sync-1 LOOP
FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference -- Generate st_sosi with sync at sop
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_symbol := v_symbol + c_nof_symbols_per_block;
FOR J IN 0 TO c_nof_block_per_sync-2 LOOP
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
v_symbol := v_symbol + c_nof_symbols_per_block; v_symbol := v_symbol + c_nof_symbols_per_block;
END LOOP; END LOOP;
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, c_nof_symbols_per_block, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_symbol := v_symbol + c_nof_symbols_per_block;
END LOOP; END LOOP;
st_sosi <= c_dp_sosi_rst; st_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(clk, 15);
tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
st_sosi_dly <= st_sosi WHEN rising_edge(clk);
-- Time stimuli -- Time stimuli
bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.sync='1'; bsn <= bsn + 1 WHEN rising_edge(clk) AND st_sosi.sync='1';
-- Add BSN to the ST data -- Add BSN to the ST data
p_in_sosi : PROCESS(st_sosi, bsn) p_in_sosi : PROCESS(st_sosi, st_sosi_dly, bsn)
BEGIN BEGIN
in_sosi <= st_sosi; in_sosi <= st_sosi_dly; -- data
in_sosi.bsn <= TO_DP_BSN(bsn); in_sosi.bsn <= TO_DP_BSN(bsn); -- bsn at sop
in_sosi.sync <= st_sosi.sync; -- sync before sop
END PROCESS; END PROCESS;
u_dut : ENTITY work.aduh_power_sum u_dut : ENTITY work.aduh_power_sum
......
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