The DDR4 IP/mem model simulation about 40x slower than that for DDR3.

libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd

@@ -82,7 +82,7 @@ BEGIN
     u_sequencer_16_1                : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns,  5 ns, 5 ns,  4,   64, 9,16, 1,  1, "VAL") PORT MAP (tb_end_vec(9));
   END GENERATE;
   
-  -- Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower
+  -- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
   gen_ddr4 : IF c_tech_ddr.name="DDR4" GENERATE
     u_sequencer_1_16                : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns,  5 ns, 5 ns,  4,   64, 9, 1,16,  1, "VAL") PORT MAP (tb_end_vec(0));
   END GENERATE;