From 1a9bb01bef4f9596d48ecfe5c127a4456e5c6efc Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 22 Jan 2015 14:06:00 +0000
Subject: [PATCH] The DDR4 IP/mem model simulation about 40x slower than that
for DDR3.
---
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index e783fb7ed9..02eaac579d 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -82,7 +82,7 @@ BEGIN
u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 4, 64, 9,16, 1, 1, "VAL") PORT MAP (tb_end_vec(9));
END GENERATE;
- -- Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower
+ -- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
gen_ddr4 : IF c_tech_ddr.name="DDR4" GENERATE
u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 4, 64, 9, 1,16, 1, "VAL") PORT MAP (tb_end_vec(0));
END GENERATE;
--
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