update

boards/uniboard2/designs/unb2_minimal/doc/README

 Quick steps to compile and use design [unb2_minimal] in RadionHDL
 -----------------------------------------------------------------
 
+-> In case of a new installation, the IP's have to be generated for Arria10.
+   In the: $RADIOHDL/libraries/technology/ip_arria10
+   directory; run the bash script: ./generate-all-ip.sh
 
 
 Start with the Oneclick Commands:
     python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
     python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2
 
+
 Generate MMM for QSYS:
     run_qsys unb2 unb2_minimal
 
+
+
 -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
 
 Simulation
@@ -28,7 +34,7 @@ Modelsim instructions:
 
     # while the simulation runs... in another bash session do:
     cd unb2_minimal/tb/python
-    python tc_unb2_minimal.py --sim --unb 0 --bn 3 --seq INFO,PPSH,SENSORS 
+    python tc_unb2_minimal.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
 
     # (sensor results only show up after 1000us of simulation runtime)
 
@@ -38,26 +44,64 @@ Modelsim instructions:
 
 Synthesis
 ---------
-Quartus instructions (for QSYS):
-    run_app unb2 unb2_minimal use=gen2
+Quartus instructions:
     run_qcomp unb2 unb2_minimal
 
-In case of needing the Quartus GUI:
+
+In case of needing the Quartus GUI for inspection:
     run_quartus unb2
 
 
-Convert .sof to .rbf:
-    run_rbf unb2 unb2_minimal  # QSYS
 
+4. Load firmware
+----------------
+Using JTAG: Start the Quartus GUI and open: tools->programmer.
+            Then click auto-detect;
+            Use 'change file' to select the correct .sof file for each FPGA
+            Select the FPGA(s) which has to be programmed
+            Click 'start'
+Using EPCS: See step 6 below.
 
-Send to LCU capture5:
-    scp $RADIOHDL/build/quartus/unb2_minimal/unb2_minimal.rbf capture5:~/rbf/  # QSYS
 
-    # Now login on capture5 and use pythonscript to program flash:
-    cd unb2_minimal/tb/python
 
-    # for example use frontnode 0 on uniboard 0:
-    python tc_unb2_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_minimal.rbf   # QSYS
 
-    python tc_unb2_minimal.py --gn 0 --seq REMU,REGMAP,INFO,PPSH,SENSORS  # start design, read info-ppsh-sensors
+5. Testing on hardware
+----------------------
+Assuming the firmware is loaded and running already in the FPGA, the firmware can be tested from the connected
+LCU computer.
+
+# (assume that the Uniboard is --unb 1)
+
+# To read out the design_name, ppsh and sensors; do:
+
+python tc_unb2_minimal.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
+
+
+
+6.
+Programming the EPCS flash.
+when the EPCS module works an RBF file can be generated to program the flash,
+then the .sof file file can be converted to .rbf with the 'run_rbf' script.
 
+But for now the only way to program the EPCS flash is via JTAG.
+Firstly a JIC file has to be generated from the SOF file.
+In Quartus GUI; open current project; File -> Convert Programming Files.
+Then setup:
+- Output programming file: JIC
+- Configuration device: EPCQL1024
+- Mode: Active Serial x4
+- Flash Loader: Add/Select Device Arria10/10AX115U4ES
+- SOF Data: add file (the generated .sof file)
+  - click the .sof file; Set property 'Compression' to ON
+- Press 'Generate'
+Then program the .JIC file (output_file.jic) to EPCS flash:
+- Make sure that the JTAG (on server connected to board) runs at 16MHz:
+  c:\altera\15.0\quartus\bin64\jtagconfig USB-BlasterII JtagClock 16M
+- open tools->programmer
+- make sure the 4 fpga icons have the device 10AX115U4F45ES
+- right-click each fpga icon and attach flash device EPCQL1024
+- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
+  (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+- right-click each EPCQL1024 and change file from <none> to output_file.jic
+- select click each Program/Configure radiobutton
+- click start and wait for 'Successful'

boards/uniboard2/designs/unb2_test/doc/README

@@ -16,6 +16,9 @@ The following revisions are available for unb2_test (see the directories in ../r
    In the: $RADIOHDL/libraries/technology/ip_arria10 
    directory; run the bash script: ./generate-all-ip.sh
 
+-> For compilation it might be necessary to check the .vhd file:
+   $RADIOHDL/libraries/technology/technology_select_pkg.vhd
+
 
 1. Start with the Oneclick Commands:
     python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t unb2
@@ -92,4 +95,15 @@ Then setup:
 - SOF Data: add file (the generated .sof file)
   - click the .sof file; Set property 'Compression' to ON
 - Press 'Generate'
+Then program the .JIC file (output_file.jic) to EPCS flash:
+- Make sure that the JTAG (on server connected to board) runs at 16MHz:
+  c:\altera\15.0\quartus\bin64\jtagconfig USB-BlasterII JtagClock 16M
+- open tools->programmer
+- make sure the 4 fpga icons have the device 10AX115U4F45ES
+- right-click each fpga icon and attach flash device EPCQL1024
+- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
+  (in $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus)
+- right-click each EPCQL1024 and change file from <none> to output_file.jic
+- select click each Program/Configure radiobutton
+- click start and wait for 'Successful'
 

libraries/technology/ip_arria10/ddr4_4g_1600/doc/README_ddr4.txt

-Tue Jul 21 18:00:02 CEST 2015
 
 Instructions of how to set the fields in the IP catalog for ddr4.qsys