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Commit 19b028f3 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'L2SDP-1005e' into 'master'

Do not assign default value for g_reset in common_fifo_sc. To avoid clutter in...

Closes L2SDP-1005

See merge request !418
parents 8bf87294 9fc2a68a
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1 merge request!418Do not assign default value for g_reset in common_fifo_sc. To avoid clutter in...
Pipeline #90693 passed
...@@ -79,6 +79,7 @@ begin ...@@ -79,6 +79,7 @@ begin
-- 2009 -- 2009
-- Capture asynchronous reset assertion, to also support i_rst when there is -- Capture asynchronous reset assertion, to also support i_rst when there is
-- no clk. -- no clk.
without_pipe : if g_tree_len = 0 generate
u_async : entity work.common_async u_async : entity work.common_async
generic map ( generic map (
g_rst_level => c_out_rst_level, g_rst_level => c_out_rst_level,
...@@ -88,20 +89,31 @@ begin ...@@ -88,20 +89,31 @@ begin
rst => i_rst, rst => i_rst,
clk => clk, clk => clk,
din => c_out_rst_level_n, din => c_out_rst_level_n,
dout => o_rst dout => out_rst
); );
end generate;
-- 2024 -- 2024
-- Pass on synchronized reset with sufficient g_tree_len to ease timing -- Pass on synchronized reset with sufficient g_tree_len to ease timing
-- closure by FF duplication in out_rst tree. Keep rst = '0' to break -- closure by FF duplication in out_rst tree. Keep rst = '0' to break
-- combinatorial path with in_rst to ease timing closure in the reset tree -- combinatorial path with in_rst to ease timing closure in the reset tree
-- network. Use g_tree_len = 0 for wire out_rst <= o_rst, so no reset tree -- network. Use g_tree_len = 0 for no clocked reset tree as in 2009.
-- as in 2009. -- Instantiate u_async again to keep 2009 and 2024 completely independent.
no_pipe : if g_tree_len = 0 generate -- To avoid delta-cycle differences due to e.g. out_rst <= o_rst when
out_rst <= o_rst; -- wires -- g_tree_len = 0, that could lead to different results in a simulation tb.
end generate; with_pipe : if g_tree_len > 0 generate
u_async : entity work.common_async
generic map (
g_rst_level => c_out_rst_level,
g_delay_len => g_delay_len
)
port map (
rst => i_rst,
clk => clk,
din => c_out_rst_level_n,
dout => o_rst
);
gen_pipe : if g_tree_len > 0 generate
u_pipe : entity work.common_async u_pipe : entity work.common_async
generic map ( generic map (
g_rst_level => c_out_rst_level, g_rst_level => c_out_rst_level,
......
...@@ -75,7 +75,8 @@ begin ...@@ -75,7 +75,8 @@ begin
u_wr_rst : entity work.common_areset u_wr_rst : entity work.common_areset
generic map ( generic map (
g_rst_level => '1', g_rst_level => '1',
g_delay_len => 3 g_delay_len => 3,
g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst
) )
port map ( port map (
in_rst => rst, in_rst => rst,
......
...@@ -94,7 +94,8 @@ begin ...@@ -94,7 +94,8 @@ begin
u_wr_rst : entity work.common_areset u_wr_rst : entity work.common_areset
generic map ( generic map (
g_rst_level => '1', g_rst_level => '1',
g_delay_len => 3 g_delay_len => 3,
g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst
) )
port map ( port map (
in_rst => rst, in_rst => rst,
......
...@@ -83,7 +83,8 @@ begin ...@@ -83,7 +83,8 @@ begin
u_fifo_rst : entity work.common_areset u_fifo_rst : entity work.common_areset
generic map ( generic map (
g_rst_level => '1', g_rst_level => '1',
g_delay_len => 4 g_delay_len => 4,
g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst
) )
port map ( port map (
in_rst => rst, in_rst => rst,
......
...@@ -368,8 +368,6 @@ begin ...@@ -368,8 +368,6 @@ begin
u_sync_bsn_fifo : entity common_lib.common_fifo_sc u_sync_bsn_fifo : entity common_lib.common_fifo_sc
generic map ( generic map (
g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep. g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep.
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w, g_dat_w => c_dp_stream_bsn_w,
g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko) g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko)
) )
......
...@@ -96,8 +96,6 @@ begin ...@@ -96,8 +96,6 @@ begin
u_bsn_fifo : entity common_lib.common_fifo_sc u_bsn_fifo : entity common_lib.common_fifo_sc
generic map ( generic map (
g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w, g_dat_w => c_dp_stream_bsn_w,
g_nof_words => c_ctrl_fifo_depth g_nof_words => c_ctrl_fifo_depth
) )
...@@ -120,8 +118,6 @@ begin ...@@ -120,8 +118,6 @@ begin
u_error_fifo : entity common_lib.common_fifo_sc u_error_fifo : entity common_lib.common_fifo_sc
generic map ( generic map (
g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_error_w, g_dat_w => c_dp_stream_error_w,
g_nof_words => c_ctrl_fifo_depth g_nof_words => c_ctrl_fifo_depth
) )
...@@ -144,8 +140,6 @@ begin ...@@ -144,8 +140,6 @@ begin
u_sync_bsn_fifo : entity common_lib.common_fifo_sc u_sync_bsn_fifo : entity common_lib.common_fifo_sc
generic map ( generic map (
g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep.
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w, g_dat_w => c_dp_stream_bsn_w,
g_nof_words => 2 g_nof_words => 2
) )
......
...@@ -158,7 +158,7 @@ begin ...@@ -158,7 +158,7 @@ begin
proc_common_gen_data(c_rl, c_init, rst, s_clk, cnt_en, ready, in_dat, in_val); proc_common_gen_data(c_rl, c_init, rst, s_clk, cnt_en, ready, in_dat, in_val);
-- Verify data -- Verify data
verify_data_en <= verify_en or dp_locked; verify_data_en <= verify_en and dp_locked;
verify_phase_en <= verify_en; verify_phase_en <= verify_en;
proc_common_verify_data(c_rl, dp_sclk, verify_data_en, ready, dp_val, dp_sample_dat, prev_dp_sample_dat); proc_common_verify_data(c_rl, dp_sclk, verify_data_en, ready, dp_val, dp_sample_dat, prev_dp_sample_dat);
......
...@@ -324,8 +324,6 @@ begin ...@@ -324,8 +324,6 @@ begin
u_sync_bsn_fifo : entity common_lib.common_fifo_sc u_sync_bsn_fifo : entity common_lib.common_fifo_sc
generic map ( generic map (
g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep. g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep.
g_reset => false,
g_init => false,
g_dat_w => c_dp_stream_bsn_w, g_dat_w => c_dp_stream_bsn_w,
g_nof_words => 16 g_nof_words => 16
) )
......
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