diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd index f2e4286f54812b5d2d7f7859494ee7bf67a572fe..a1ee86812bf3c6d3d2d53233be9f5f3043b9b7bf 100644 --- a/libraries/base/common/src/vhdl/common_areset.vhd +++ b/libraries/base/common/src/vhdl/common_areset.vhd @@ -79,29 +79,41 @@ begin -- 2009 -- Capture asynchronous reset assertion, to also support i_rst when there is -- no clk. - u_async : entity work.common_async - generic map ( - g_rst_level => c_out_rst_level, - g_delay_len => g_delay_len - ) - port map ( - rst => i_rst, - clk => clk, - din => c_out_rst_level_n, - dout => o_rst - ); + without_pipe : if g_tree_len = 0 generate + u_async : entity work.common_async + generic map ( + g_rst_level => c_out_rst_level, + g_delay_len => g_delay_len + ) + port map ( + rst => i_rst, + clk => clk, + din => c_out_rst_level_n, + dout => out_rst + ); + end generate; -- 2024 -- Pass on synchronized reset with sufficient g_tree_len to ease timing -- closure by FF duplication in out_rst tree. Keep rst = '0' to break -- combinatorial path with in_rst to ease timing closure in the reset tree - -- network. Use g_tree_len = 0 for wire out_rst <= o_rst, so no reset tree - -- as in 2009. - no_pipe : if g_tree_len = 0 generate - out_rst <= o_rst; -- wires - end generate; + -- network. Use g_tree_len = 0 for no clocked reset tree as in 2009. + -- Instantiate u_async again to keep 2009 and 2024 completely independent. + -- To avoid delta-cycle differences due to e.g. out_rst <= o_rst when + -- g_tree_len = 0, that could lead to different results in a simulation tb. + with_pipe : if g_tree_len > 0 generate + u_async : entity work.common_async + generic map ( + g_rst_level => c_out_rst_level, + g_delay_len => g_delay_len + ) + port map ( + rst => i_rst, + clk => clk, + din => c_out_rst_level_n, + dout => o_rst + ); - gen_pipe : if g_tree_len > 0 generate u_pipe : entity work.common_async generic map ( g_rst_level => c_out_rst_level, diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd index 84d9f3e6ad18ac66e24c19b693875ffc835dd17c..e14f425292aaaee5e0bd97b513a2af8427357f75 100644 --- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd +++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd @@ -75,7 +75,8 @@ begin u_wr_rst : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 3 + g_delay_len => 3, + g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst ) port map ( in_rst => rst, diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd index 01a58b14b26314dca674a65db1c631d318acdf7e..f8e00f24c557d2b78b319d3e24a5308d838d851e 100644 --- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd +++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd @@ -94,7 +94,8 @@ begin u_wr_rst : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 3 + g_delay_len => 3, + g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst ) port map ( in_rst => rst, diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd index db6cc9302b77964cc13b3efa1caf911df8b3f03b..117e229b281ec810f9e12ef8deb42b85dbfcd55a 100644 --- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd +++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd @@ -83,7 +83,8 @@ begin u_fifo_rst : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 4 + g_delay_len => 4, + g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst ) port map ( in_rst => rst, diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd index 87dcb12eb142c5d53e00317da795fa008325dae2..ecf317c77fd17dd47c98d402b590d1b94697b41f 100644 --- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd +++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd @@ -368,8 +368,6 @@ begin u_sync_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko) ) diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd index 500b07e8b6b3f4604f1c70b802801cb80d4d9a2c..ae5d36ad86eefcb87632d611b3b4f45687dcef8e 100644 --- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd +++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd @@ -96,8 +96,6 @@ begin u_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => c_ctrl_fifo_depth ) @@ -120,8 +118,6 @@ begin u_error_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_error_w, g_nof_words => c_ctrl_fifo_depth ) @@ -144,8 +140,6 @@ begin u_sync_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => 2 ) diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd index 4b486c78604c56df55dafdb845af7b523e38ce8f..cc84dee71bea2d11a30c2d2ed42ce8f050739ebe 100644 --- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd +++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd @@ -158,7 +158,7 @@ begin proc_common_gen_data(c_rl, c_init, rst, s_clk, cnt_en, ready, in_dat, in_val); -- Verify data - verify_data_en <= verify_en or dp_locked; + verify_data_en <= verify_en and dp_locked; verify_phase_en <= verify_en; proc_common_verify_data(c_rl, dp_sclk, verify_data_en, ready, dp_val, dp_sample_dat, prev_dp_sample_dat); diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd index 7909a2d68922b9044c750a5b63eabd4ad238ce82..b4ec6773d01b13f8c41c131dbe2cdcaac25da021 100644 --- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd +++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd @@ -324,8 +324,6 @@ begin u_sync_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => 16 )