From 196509eba7a844cd173b12be84797c21883c3d53 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 29 May 2015 13:29:05 +0000
Subject: [PATCH] -Added inc_comb.py + description in readme_myHDL.txt.
---
tools/oneclick/prestudy/myHDL/inc_comb.py | 32 +++++++++++++++++++
.../oneclick/prestudy/myHDL/readme_myHDL.txt | 3 +-
2 files changed, 34 insertions(+), 1 deletion(-)
create mode 100644 tools/oneclick/prestudy/myHDL/inc_comb.py
diff --git a/tools/oneclick/prestudy/myHDL/inc_comb.py b/tools/oneclick/prestudy/myHDL/inc_comb.py
new file mode 100644
index 0000000000..942a37b47c
--- /dev/null
+++ b/tools/oneclick/prestudy/myHDL/inc_comb.py
@@ -0,0 +1,32 @@
+from myhdl import *
+
+def inc_comb(nextCount, count, n):
+
+ @always(count)
+ def logic():
+ # do nothing here
+ pass
+
+ nextCount.driven = "wire"
+
+ return logic
+
+inc_comb.verilog_code =\
+"""
+assign $nextCount = ($count + 1) % $n;
+"""
+
+inc_comb.vhdl_code =\
+"""
+$nextCount <= ($count + 1) mod $n;
+"""
+
+def convert():
+
+ nextCount = Signal(intbv(0)[8:])
+ count = Signal(intbv(0)[8:])
+
+ toVerilog(inc_comb, nextCount, count, 256 )
+ toVHDL(inc_comb, nextCount, count, 256)
+
+convert()
diff --git a/tools/oneclick/prestudy/myHDL/readme_myHDL.txt b/tools/oneclick/prestudy/myHDL/readme_myHDL.txt
index bc49d7e4d5..daf7869353 100644
--- a/tools/oneclick/prestudy/myHDL/readme_myHDL.txt
+++ b/tools/oneclick/prestudy/myHDL/readme_myHDL.txt
@@ -24,4 +24,5 @@ This dir contains:
-> Creates tb_muxed_block_gens.v (template TB file)
-> Creates pck_myhdl_081.vhd (a package file)
-> Creates muxed_block_gens.vhd
-
+-inc_comb.py: example code from the myHDL Manual, but completed so it generates
+ output files. It demonstrates how to include user defined code.
--
GitLab