Added dp_fifo_sc and dp_fifo_dc that now use dp_fifo_core.vhd.

libraries/base/dp/src/vhdl/dp_fifo_dc.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
+-- Description: See dp_fifo_core.vhd.
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_fifo_dc IS
+  GENERIC (
+    g_data_w         : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+    g_bsn_w          : NATURAL := 1;
+    g_empty_w        : NATURAL := 1;
+    g_channel_w      : NATURAL := 1;
+    g_error_w        : NATURAL := 1;
+    g_use_bsn        : BOOLEAN := FALSE;
+    g_use_empty      : BOOLEAN := FALSE;
+    g_use_channel    : BOOLEAN := FALSE;
+    g_use_error      : BOOLEAN := FALSE;
+    g_use_sync       : BOOLEAN := FALSE;
+    g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
+    g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+    g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_rl        : NATURAL := 1
+  );
+  PORT (
+    wr_rst      : IN  STD_LOGIC;
+    wr_clk      : IN  STD_LOGIC;
+    rd_rst      : IN  STD_LOGIC;
+    rd_clk      : IN  STD_LOGIC;
+    -- Monitor FIFO filling
+    wr_ful      : OUT STD_LOGIC;
+    wr_usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+    rd_usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+    rd_emp      : OUT STD_LOGIC;
+    -- ST sink
+    snk_out     : OUT t_dp_siso;
+    snk_in      : IN  t_dp_sosi;
+    -- ST source
+    src_in      : IN  t_dp_siso;
+    src_out     : OUT t_dp_sosi
+  );
+END dp_fifo_dc;
+
+
+ARCHITECTURE str OF dp_fifo_dc IS
+BEGIN
+
+  u_dp_fifo_core : ENTITY work.dp_fifo_core
+  GENERIC MAP (
+    g_use_dual_clock => TRUE,
+    g_data_w         => g_data_w,
+    g_bsn_w          => g_bsn_w,
+    g_empty_w        => g_empty_w,
+    g_channel_w      => g_channel_w,
+    g_error_w        => g_error_w,
+    g_use_bsn        => g_use_bsn, 
+    g_use_empty      => g_use_empty,
+    g_use_channel    => g_use_channel,
+    g_use_error      => g_use_error,
+    g_use_sync       => g_use_sync,
+    g_use_ctrl       => g_use_ctrl,
+    g_use_complex    => g_use_complex,
+    g_fifo_size      => g_fifo_size,
+    g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_rl        => g_fifo_rl
+  )
+  PORT MAP (
+    wr_rst      => wr_rst,
+    wr_clk      => wr_clk,
+    rd_rst      => rd_rst,
+    rd_clk      => rd_clk,
+    -- Monitor FIFO filling
+    wr_ful      => wr_ful,
+    wr_usedw    => wr_usedw,
+    rd_usedw    => rd_usedw,
+    rd_emp      => rd_emp,
+    -- ST sink
+    snk_out     => snk_out,
+    snk_in      => snk_in,
+    -- ST source
+    src_in      => src_in,
+    src_out     => src_out
+  );
+
+END str;

libraries/base/dp/src/vhdl/dp_fifo_sc.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose: DP FIFO for single clock (= sc) domain wr and rd.
+-- Description: See dp_fifo_core.vhd.
+
+LIBRARY IEEE,common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_fifo_sc IS
+  GENERIC (
+    g_data_w         : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+    g_bsn_w          : NATURAL := 1;
+    g_empty_w        : NATURAL := 1;
+    g_channel_w      : NATURAL := 1;
+    g_error_w        : NATURAL := 1;
+    g_use_bsn        : BOOLEAN := FALSE;
+    g_use_empty      : BOOLEAN := FALSE;
+    g_use_channel    : BOOLEAN := FALSE;
+    g_use_error      : BOOLEAN := FALSE;
+    g_use_sync       : BOOLEAN := FALSE;
+    g_use_ctrl       : BOOLEAN := TRUE;  -- sop & eop
+    g_use_complex    : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+    g_fifo_size      : NATURAL := 512;   -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+    g_fifo_af_margin : NATURAL := 4;     -- >=4, Nof words below max (full) at which fifo is considered almost full
+    g_fifo_rl        : NATURAL := 1
+  );
+  PORT (
+    rst         : IN  STD_LOGIC;
+    clk         : IN  STD_LOGIC;
+    -- Monitor FIFO filling
+    wr_ful      : OUT STD_LOGIC;
+    usedw       : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+    rd_emp      : OUT STD_LOGIC;
+    -- ST sink
+    snk_out     : OUT t_dp_siso;
+    snk_in      : IN  t_dp_sosi;
+    -- ST source
+    src_in      : IN  t_dp_siso;
+    src_out     : OUT t_dp_sosi
+  );
+END dp_fifo_sc;
+
+
+ARCHITECTURE str OF dp_fifo_sc IS
+BEGIN
+
+  u_dp_fifo_core : ENTITY work.dp_fifo_core
+  GENERIC MAP (
+    g_use_dual_clock => FALSE,
+    g_data_w         => g_data_w,
+    g_bsn_w          => g_bsn_w,
+    g_empty_w        => g_empty_w,
+    g_channel_w      => g_channel_w,
+    g_error_w        => g_error_w,
+    g_use_bsn        => g_use_bsn, 
+    g_use_empty      => g_use_empty,
+    g_use_channel    => g_use_channel,
+    g_use_error      => g_use_error,
+    g_use_sync       => g_use_sync,
+    g_use_ctrl       => g_use_ctrl,
+    g_use_complex    => g_use_complex,
+    g_fifo_size      => g_fifo_size,
+    g_fifo_af_margin => g_fifo_af_margin,
+    g_fifo_rl        => g_fifo_rl
+  )
+  PORT MAP (
+    wr_rst      => rst,
+    wr_clk      => clk,
+    rd_rst      => rst,
+    rd_clk      => clk,
+    -- Monitor FIFO filling
+    wr_ful      => wr_ful,
+    wr_usedw    => OPEN,
+    rd_usedw    => usedw,
+    rd_emp      => rd_emp,
+    -- ST sink
+    snk_out     => snk_out,
+    snk_in      => snk_in,
+    -- ST source
+    src_in      => src_in,
+    src_out     => src_out
+  );
+
+END str;