Ported dp_dummy_source.vhd to match init data width of 576 bits all filled with 0xD.

libraries/base/dp/hdllib.cfg

@@ -29,9 +29,9 @@ synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_shiftreg.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_info.vhd
     src/vhdl/dp_fifo_core.vhd
-    dp/src/vhdl/dp_fifo_sc.vhd
+    src/vhdl/dp_fifo_sc.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_fill.vhd
-    dp/src/vhdl/dp_fifo_dc.vhd
+    src/vhdl/dp_fifo_dc.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
     src/vhdl/dp_fifo_fill_core.vhd
     src/vhdl/dp_fifo_fill_sc.vhd
@@ -94,7 +94,7 @@ synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_packet_merge.vhd
     $UNB/Firmware/modules/dp/src/vhdl/mms_dp_packet_merge.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_packet_unmerge.vhd
-    $UNB/Firmware/modules/dp/src/vhdl/dp_dummy_source.vhd
+    src/vhdl/dp_dummy_source.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_field_blk.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_offload_tx.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_offload_tx_len_calc.vhd

libraries/base/dp/src/vhdl/dp_dummy_source.vhd

+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose : 
+--   Provide packetized dummy values when sink is ready
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_dummy_source IS
+  GENERIC (
+    g_dummy_nof_data   : NATURAL := 100; -- Nof words per block
+    g_dummy_bsn        : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0)      := x"DDDDDDDD_DDDDDDDD";
+    g_dummy_data       : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0)     := x"DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD_DDDDDDDD";
+    g_dummy_re         : STD_LOGIC_VECTOR(c_dp_stream_dsp_data_w-1 DOWNTO 0) := x"DDDDDDDD_DDDDDDDD";
+    g_dummy_im         : STD_LOGIC_VECTOR(c_dp_stream_dsp_data_w-1 DOWNTO 0) := x"DDDDDDDD_DDDDDDDD";
+    g_dummy_empty      : STD_LOGIC_VECTOR(c_dp_stream_empty_w-1 DOWNTO 0)    := x"DD";
+    g_dummy_channel    : STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0)  := x"DDDDDDDD";
+    g_dummy_err        : STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0)    := x"DDDDDDDD"
+   );
+  PORT (
+    rst                : IN  STD_LOGIC;
+    clk                : IN  STD_LOGIC;
+ 
+    src_out            : OUT t_dp_sosi;
+    src_in             : IN  t_dp_siso
+  );
+END dp_dummy_source;
+
+
+ARCHITECTURE rtl OF dp_dummy_source IS
+
+  CONSTANT c_dp_sosi_dummy : t_dp_sosi := ('0', g_dummy_bsn, g_dummy_data, g_dummy_re, g_dummy_im, '0', '0', '0', g_dummy_empty, g_dummy_channel, g_dummy_err);
+
+  SIGNAL block_sosi : t_dp_sosi;  
+ 
+BEGIN
+
+  src_out.valid   <= block_sosi.valid; 
+  src_out.sop     <= block_sosi.sop;
+  src_out.eop     <= block_sosi.eop;
+ 
+  src_out.sync    <= c_dp_sosi_dummy.sync;
+  src_out.data    <= c_dp_sosi_dummy.data;
+  src_out.bsn     <= c_dp_sosi_dummy.bsn;
+  src_out.re      <= c_dp_sosi_dummy.re;
+  src_out.im      <= c_dp_sosi_dummy.im;
+  src_out.empty   <= c_dp_sosi_dummy.empty;
+  src_out.channel <= c_dp_sosi_dummy.channel;
+  src_out.err     <= c_dp_sosi_dummy.err;
+
+  u_dp_block_gen: ENTITY work.dp_block_gen
+  GENERIC MAP (
+    g_nof_data => g_dummy_nof_data
+  )
+  PORT MAP (
+    rst        => rst,
+    clk        => clk,
+
+    src_in     => src_in,
+    src_out    => block_sosi,
+
+    en         => '1'
+  );
+
+END rtl;
+