Merge branch 'STAT-266' into 'master'

Resolve STAT-266

Closes STAT-266

See merge request desp/hdl!13

boards/uniboard2b/designs/unb2b_arp_ping/doc/README

+Quick steps to compile and use design [unb2b_minimal] in RadionHDL
+------------------------------------------------------------------
+
+On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
+
+
+-> In case of a new installation, the IP's have to be generated for Arria10.
+   In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
+   directory; run the bash script: ./generate-all-ip.sh
+
+-> For compilation it might be necessary to check the .vhd file:
+   $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+
+-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
+
+-> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
+
+1. Start with the Oneclick Commands:
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+
+# 2. Generate MMM for QSYS:
+#     run_qsys unb2b unb2b_minimal
+
+3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
+
+Simulation
+----------
+Modelsim instructions:
+    # in bash do:
+    rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
+    run_modelsim unb2b
+
+    # in Modelsim do:
+    lp unb2b_minimal
+    mk all
+    # now double click on testbench file
+    as 10
+    run 500us
+
+    # while the simulation runs... in another bash session do:
+    cd unb2b_minimal/tb/python
+    python tc_unb2b_minimal.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
+
+    # (sensor results only show up after 1000us of simulation runtime)
+
+    # to end simulation in Modelsim do:
+    quit -sim
+
+
+Synthesis
+---------
+# Quartus instructions:
+#     run_qcomp unb2 unb2b_minimal
+
+
+# scripts are not yet working for quartus 17.0.2, this is the workaround.
+- "run_quartus unb2b &"
+- Open the unb2b_minumal quartus project from the build directory.
+- Open the qsys_unb2b_minimal.qsys file from the build directory.
+- Generate the HDL files for the qsys using the GUI.
+- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
+- "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
+- "run_app unb2b unb2b_minimal use=gen2"
+- In Quartus, click the play button to compile the design.
+
+if project ip's are missing problably /home/[user name]/.altera.quartus/ip/17.0.2/ is missing. 
+ (just make a copy of the previous one and rename it)
+
+
+4. Load firmware
+----------------
+Using JTAG: Start the Quartus GUI and open: tools->programmer.
+            Then click auto-detect;
+            Use 'change file' to select the correct .sof file for each FPGA
+            Select the FPGA(s) which has to be programmed
+            Click 'start'
+Using EPCS: See step 6 below.
+
+
+
+
+5. Testing on hardware
+----------------------
+Assuming the firmware is loaded and running already in the FPGA, the firmware can be tested from the connected
+LCU computer.
+
+# (assume that the Uniboard is --unb 1)
+
+# To read out the design_name, ppsh and sensors; do:
+
+python tc_unb2_minimal.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
+
+
+
+6. Programming the EPCS flash.
+------------------------------
+On an empty new board the factory image must be loaded using the programmer and a yic file.
+
+when the EPCS module works (factory image is loaded in flash) an RBF file can be generated to program the flash,
+then the .sof file file can be converted to .rbf with the 'run_rbf' script.
+
+But for now the only way to program the EPCS flash is via JTAG.
+Firstly a JIC file has to be generated from the SOF file.
+In Quartus GUI; open current project; File -> Convert Programming Files.
+Then setup:
+- Output programming file: JIC
+- Configuration device: EPCQ-L1024
+- Mode: Active Serial x4
+- Flash Loader: Add/Select Device Arria10 / 10AX115U2
+- SOF Data: add file (the generated .sof file)
+  - click the .sof file; Set property 'Compression' to ON
+- Press 'Generate'
+- Press "Done"
+
+In Quartus GUI:
+Setup Device (if needed):
+- click in menu: 'Assignments' -> 'Device'
+- Name: 10AX115U2F45E1SG
+- click 'Device and Pin Options' button.
+- Configuration scheme: Active Serial x4
+- check Use Configuration device: EPCQL1024.
+- Configuration device I/O voltage: 1.8V
+- check Generate compressed bitstreams.
+- Active clock source: 12.5 MHz Internal Oscillator.
+
+Then program the .JIC file (output_file.jic) to EPCS flash:
+- Make sure that the JTAG (on server connected to board) runs at 16MHz:
+  /home/software/software/Altera/17.0/quartus/bin/jtagconfig USB-BlasterII JtagClock 16M
+- open tools->programmer
+- make sure the 4 fpga icons have the device 10AX115U2F45
+- right-click each fpga icon and attach flash device EPCQ-L1024
+- right-click each EPCQ-L1024 and change file from <none> to output_file.jic
+- check each Program/Configure radiobutton for the EPCQ-L1024, the right 'sfl' file is auto selected and checked. 
+- click start and wait for 'Successful'
+- restart the board by toggling the button on the front (only needed the first time)

boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg

+hdl_lib_name = unb2b_arp_ping
+hdl_library_clause_name = unb2b_arp_ping_lib
+hdl_lib_uses_synth = common technology mm unb2b_board eth1g tech_tse
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    src/vhdl/unb2b_arp_ping.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_unb2b_arp_ping.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files = 
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus .
+
+quartus_qsf_files =
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    quartus/unb2b_minimal_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+
+quartus_ip_files =