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RTSD
HDL
Commits
133cec37
Commit
133cec37
authored
Jun 28, 2022
by
Eric Kooistra
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Add rd_input_delay, to see that mm_rst_jesd only needs to be applied to the u_jesd204b.
parent
fb7636a2
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1 merge request
!263
Resolve L2SDP-755
Pipeline
#32560
failed
Jun 28, 2022
Stage: simulation
Stage: synthesis
Stage: hardware
Changes
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applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+29
-1
29 additions, 1 deletion
..._sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
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29 additions
and
1 deletion
applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+
29
−
1
View file @
133cec37
...
@@ -49,6 +49,8 @@
...
@@ -49,6 +49,8 @@
-- > as 16 # for detailed debugging of JESD204B IP
-- > as 16 # for detailed debugging of JESD204B IP
-- > run -a
-- > run -a
--
--
-- View ait_sosi_arr, to see that only complete blocks are passed on.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY
IEEE
,
common_lib
,
unb2c_board_lib
,
i2c_lib
,
mm_lib
,
dp_lib
,
diag_lib
,
lofar2_sdp_lib
,
wpfb_lib
,
lofar2_unb2c_sdp_station_lib
,
tech_jesd204b_lib
;
LIBRARY
IEEE
,
common_lib
,
unb2c_board_lib
,
i2c_lib
,
mm_lib
,
dp_lib
,
diag_lib
,
lofar2_sdp_lib
,
wpfb_lib
,
lofar2_unb2c_sdp_station_lib
,
tech_jesd204b_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
std_logic_1164
.
ALL
;
...
@@ -114,6 +116,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS
...
@@ -114,6 +116,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS
CONSTANT
c_mm_file_reg_bsn_scheduler_wg
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_BSN_SCHEDULER"
;
CONSTANT
c_mm_file_reg_bsn_scheduler_wg
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_BSN_SCHEDULER"
;
CONSTANT
c_mm_file_reg_diag_wg
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_WG"
;
CONSTANT
c_mm_file_reg_diag_wg
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_WG"
;
CONSTANT
c_mm_file_reg_aduh_mon
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_ADUH_MONITOR"
;
CONSTANT
c_mm_file_reg_aduh_mon
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_ADUH_MONITOR"
;
CONSTANT
c_mm_file_reg_dp_shiftram
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"REG_DP_SHIFTRAM"
;
CONSTANT
c_mm_file_jesd204b
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"JESD204B"
;
CONSTANT
c_mm_file_jesd204b
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"JESD204B"
;
CONSTANT
c_mm_file_pio_jesd_ctrl
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"PIO_JESD_CTRL"
;
CONSTANT
c_mm_file_pio_jesd_ctrl
:
STRING
:
=
mmf_unb_file_prefix
(
c_unb_nr
,
c_node_nr
)
&
"PIO_JESD_CTRL"
;
...
@@ -126,6 +129,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS
...
@@ -126,6 +129,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS
SIGNAL
pps_rst
:
STD_LOGIC
:
=
'1'
;
SIGNAL
pps_rst
:
STD_LOGIC
:
=
'1'
;
SIGNAL
gen_pps
:
STD_LOGIC
:
=
'0'
;
SIGNAL
gen_pps
:
STD_LOGIC
:
=
'0'
;
-- Input delay
SIGNAL
rd_input_delay
:
NATURAL
;
-- WG
-- WG
SIGNAL
dbg_c_exp_wg_power_sp_0
:
REAL
:
=
c_exp_wg_power_sp_0
;
SIGNAL
dbg_c_exp_wg_power_sp_0
:
REAL
:
=
c_exp_wg_power_sp_0
;
SIGNAL
sp_samples
:
t_integer_arr
(
0
TO
c_mon_buffer_nof_samples
-1
)
:
=
(
OTHERS
=>
0
);
SIGNAL
sp_samples
:
t_integer_arr
(
0
TO
c_mon_buffer_nof_samples
-1
)
:
=
(
OTHERS
=>
0
);
...
@@ -471,11 +477,21 @@ BEGIN
...
@@ -471,11 +477,21 @@ BEGIN
VARIABLE
v_sp_power_sum_0
:
REAL
;
VARIABLE
v_sp_power_sum_0
:
REAL
;
VARIABLE
v_sp_subband_power
:
REAL
;
VARIABLE
v_sp_subband_power
:
REAL
;
VARIABLE
v_W
,
v_T
,
v_U
,
v_S
,
v_B
:
NATURAL
;
-- array indicies
VARIABLE
v_W
,
v_T
,
v_U
,
v_S
,
v_B
:
NATURAL
;
-- array indicies
VARIABLE
v_exp_input_delay
:
NATURAL
;
BEGIN
BEGIN
dbg_restart
<=
0
;
dbg_restart
<=
0
;
FOR
REP
IN
0
TO
c_nof_restarts
LOOP
FOR
REP
IN
0
TO
c_nof_restarts
LOOP
-- Wait for DUT power up after reset or after AIT rx_clk domain restart
-- Wait for DUT power up after reset or after AIT rx_clk domain restart
WAIT
FOR
1
us
;
WAIT
FOR
2
us
;
----------------------------------------------------------------------------
-- Set and readback input delay for si = 0
----------------------------------------------------------------------------
v_exp_input_delay
:
=
10
+
REP
;
mmf_mm_bus_wr
(
c_mm_file_reg_dp_shiftram
,
0
,
v_exp_input_delay
,
tb_clk
);
proc_common_wait_cross_clock_domain_latency
(
tb_clk
,
ext_clk
);
mmf_mm_bus_rd
(
c_mm_file_reg_dp_shiftram
,
0
,
rd_data
,
tb_clk
);
rd_input_delay
<=
TO_UINT
(
rd_data
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Enable BS
-- Enable BS
...
@@ -615,6 +631,12 @@ BEGIN
...
@@ -615,6 +631,12 @@ BEGIN
reg_jesd204b_csr_rbd_count
,
reg_jesd204b_csr_rbd_count
,
reg_jesd204b_csr_dev_syncn
);
reg_jesd204b_csr_dev_syncn
);
-- Read input delay during reset
mmf_mm_bus_rd
(
c_mm_file_reg_dp_shiftram
,
0
,
rd_data
,
tb_clk
);
rd_input_delay
<=
TO_UINT
(
rd_data
);
proc_common_wait_some_cycles
(
tb_clk
,
1
);
ASSERT
rd_input_delay
=
v_exp_input_delay
REPORT
"wrong rd_input_delay during JESD reset."
SEVERITY
ERROR
;
-- Hold JESD_CTRL reset for > one sync period, so also during a JESD204B_SYSREF pulse,
-- Hold JESD_CTRL reset for > one sync period, so also during a JESD204B_SYSREF pulse,
-- to see that JESD_CTRL reset stops JESD204B OUT rx_sysref too.
-- to see that JESD_CTRL reset stops JESD204B OUT rx_sysref too.
WAIT
FOR
c_pps_period
;
WAIT
FOR
c_pps_period
;
...
@@ -630,6 +652,12 @@ BEGIN
...
@@ -630,6 +652,12 @@ BEGIN
pio_jesd_ctrl_reset
<=
rd_data
(
c_sdp_jesd_ctrl_reset_bi
);
pio_jesd_ctrl_reset
<=
rd_data
(
c_sdp_jesd_ctrl_reset_bi
);
dbg_jesd_ctrl_reset
<=
'0'
;
-- marker in wave window
dbg_jesd_ctrl_reset
<=
'0'
;
-- marker in wave window
-- Read input delay after reset
mmf_mm_bus_rd
(
c_mm_file_reg_dp_shiftram
,
0
,
rd_data
,
tb_clk
);
rd_input_delay
<=
TO_UINT
(
rd_data
);
proc_common_wait_some_cycles
(
tb_clk
,
1
);
ASSERT
rd_input_delay
=
v_exp_input_delay
REPORT
"wrong rd_input_delay after JESD reset."
SEVERITY
ERROR
;
-- Wait for a JESD204B_SYSREF pulse
-- Wait for a JESD204B_SYSREF pulse
WAIT
FOR
c_pps_period
;
WAIT
FOR
c_pps_period
;
-- Read Rx JESD_204B IP status
-- Read Rx JESD_204B IP status
...
...
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