Rename mm_rst_intenal into mm_rst_jesd and apply mm_rst_jesd only to the u_jesd204b.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -140,7 +140,7 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
   SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
   SIGNAL st_sosi_arr                : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);    
 
-  SIGNAL mm_rst_internal            : STD_LOGIC; 
+  SIGNAL mm_rst_jesd                : STD_LOGIC;
   SIGNAL mm_jesd_ctrl_reg           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL jesd204b_disable_arr       : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
 
@@ -152,15 +152,16 @@ BEGIN
     rx_sysref <= dp_pps;
   END GENERATE;
 
-  -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_disable_arr.
-  -- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
-  -- The MM jesd204b_disable_arr is intended for node AIT resynchronisation tests of the u_jesd204b.
-  -- The MM jesd204b_disable_arr should not be applied in an SDP application, because this will cause
+  -- The node AIT is reset at power up by mm_rst and under software control by mm_rst_jesd.
+  -- The mm_rst_jesd will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
+  -- The mm_rst_jesd is intended for node AIT resynchronisation tests of the u_jesd204b.
+  -- The mm_rst_jesd should not be applied in an active SDP application, because this will cause
   -- a disturbance in the block timing of the out_sosi_arr(i).sync,bsn,sop,eop. The other logic
   -- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
-  -- complete blocks, so from sop to eop.
+  -- complete blocks, so from sop to eop. Therefore, first mms_dp_bsn_source_v2 should be
+  -- disabled to stop and flush the block processing, before applying mm_rst_jesd.
 
-  mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(c_sdp_jesd_ctrl_reset_bi);
+  mm_rst_jesd <= mm_rst OR mm_jesd_ctrl_reg(c_sdp_jesd_ctrl_reset_bi);
   gen_jesd_disable : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
     jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
   END GENERATE;
@@ -191,7 +192,7 @@ BEGIN
     
       -- MM
       mm_clk               => mm_clk,           
-      mm_rst               => mm_rst_internal,           
+      mm_rst               => mm_rst_jesd,
     
       jesd204b_mosi        => jesd204b_mosi,         
       jesd204b_miso        => jesd204b_miso,         
@@ -232,7 +233,7 @@ BEGIN
       dp_rst   => rx_rst,
       dp_clk   => rx_clk,
   
-      mm_rst   => mm_rst_internal,
+      mm_rst   => mm_rst,
       mm_clk   => mm_clk,
   
       sync_in  => bs_sosi.sync,
@@ -258,7 +259,7 @@ BEGIN
   )
   PORT MAP (
     -- Clocks and reset
-    mm_rst            => mm_rst_internal,
+    mm_rst            => mm_rst,
     mm_clk            => mm_clk,
     dp_rst            => rx_rst,
     dp_clk            => rx_clk,
@@ -281,7 +282,7 @@ BEGIN
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst      => mm_rst_internal,
+    mm_rst      => mm_rst,
     mm_clk      => mm_clk,
 
     reg_mosi    => reg_bsn_scheduler_wg_mosi,
@@ -318,7 +319,7 @@ BEGIN
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst              => mm_rst_internal,
+    mm_rst              => mm_rst,
     mm_clk              => mm_clk,
 
     reg_mosi            => reg_wg_mosi,
@@ -387,7 +388,7 @@ BEGIN
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst      => mm_rst_internal,
+    mm_rst      => mm_rst,
     mm_clk      => mm_clk,
     reg_mosi    => reg_bsn_monitor_input_mosi,
     reg_miso    => reg_bsn_monitor_input_miso,
@@ -412,7 +413,7 @@ BEGIN
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst         => mm_rst_internal,
+    mm_rst         => mm_rst,
     mm_clk         => mm_clk,
 
     reg_mosi       => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
@@ -440,7 +441,7 @@ BEGIN
     g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
   )
   PORT MAP (
-    mm_rst            => mm_rst_internal,
+    mm_rst            => mm_rst,
     mm_clk            => mm_clk,
     dp_rst            => rx_rst,
     dp_clk            => rx_clk,
@@ -466,7 +467,7 @@ BEGIN
     g_nof_data_per_sync_diff => c_sdp_N_fft/2 
   )
   PORT MAP (
-    mm_rst            => mm_rst_internal,
+    mm_rst            => mm_rst,
     mm_clk            => mm_clk,
     dp_rst            => rx_rst,
     dp_clk            => rx_clk,