Corrected compile error.

libraries/technology/tse/tech_tse.vhd

@@ -30,7 +30,7 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 
-ENTITY tse IS
+ENTITY tech_tse IS
   GENERIC (
     g_technology   : NATURAL := c_tech_select_default;
     g_ETH_PHY      : STRING  := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
@@ -71,15 +71,15 @@ ENTITY tse IS
 
     tse_led        : OUT t_tse_led
   );
-END tse;
+END tech_tse;
 
-ARCHITECTURE str OF tech_memory_ram_crw_crw IS
+ARCHITECTURE str OF tech_tse IS
 
 BEGIN
 
   gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
     u0 : ENTITY work.tech_tse_stratixiv
-    GENERIC MAP (g_ETH_PHY);
+    GENERIC MAP (g_ETH_PHY)
     PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
               cal_rec_clk,
               mm_sla_in, mm_sla_out,