Initilal commit

applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/apertif_unb1_cor_mesh_ref.vhd

+------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+
+ENTITY apertif_unb1_cor_mesh_ref IS
+  GENERIC (
+    -- General
+    g_design_name   : STRING  := "unb1_terminal_bg_mesh_db";  
+    g_design_note   : STRING  := "UNUSED";
+    g_sim           : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_level     : NATURAL := 0; 
+    g_sim_unb_nr    : NATURAL := 0;
+    g_sim_node_nr   : NATURAL := 0;
+    g_stamp_date    : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time    : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_stamp_svn     : NATURAL := 0   -- SVN revision    -- set by QSF
+  );
+  PORT (
+   -- GENERAL
+    CLK                    : IN    STD_LOGIC; -- System Clock
+    PPS                    : IN    STD_LOGIC; -- System Sync
+    WDI                    : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA                   : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB                   : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION                : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+    ID                     : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+    TESTIO                 : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+    -- I2C Interface to Sensors
+    sens_sc                : INOUT STD_LOGIC;
+    sens_sd                : INOUT STD_LOGIC;
+
+    -- 1GbE Control Interface
+    ETH_clk                : IN    STD_LOGIC;
+    ETH_SGIN               : IN    STD_LOGIC;
+    ETH_SGOUT              : OUT   STD_LOGIC;
+    
+    -- Transceiver clocks
+    SB_CLK                 : IN  STD_LOGIC := '0';  -- TR clock FN-BN    (mesh)
+
+    -- Serial I/O
+    FN_BN_0_TX             : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_0_RX             : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+    FN_BN_1_TX             : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_1_RX             : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+    FN_BN_2_TX             : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_2_RX             : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+    FN_BN_3_TX             : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+    FN_BN_3_RX             : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0')
+  );
+END apertif_unb1_cor_mesh_ref;
+
+
+ARCHITECTURE str OF apertif_unb1_cor_mesh_ref IS
+  
+  CONSTANT c_use_phy                 : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);         
+  CONSTANT c_fw_version              : t_unb1_board_fw_version := (1, 0);  -- firmware version x.y 
+                                     
+  CONSTANT c_node_type               : t_e_unb1_board_node := e_any;   -- or e_fn, or e_bn
+  CONSTANT c_nof_bus                 : NATURAL := 4;      -- one bus to each of the 4 nodes on the other side of the mesh
+  CONSTANT c_usr_use_complex         : BOOLEAN := TRUE;   -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
+  CONSTANT c_usr_data_w              : NATURAL := 8;      -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+  CONSTANT c_usr_frame_len           : NATURAL := 128; --20;
+  CONSTANT c_usr_nof_streams         : NATURAL := 3;      -- number of user streams per bus
+  CONSTANT c_phy_nof_serial          : NATURAL := 3;      -- up to 4 serial lanes per bus
+  CONSTANT c_phy_gx_mbps             : NATURAL := 6250; --5000;
+  CONSTANT c_phy_rx_fifo_size        : NATURAL := c_bram_m9k_fifo_depth;   -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY
+  CONSTANT c_phy_ena_reorder         : BOOLEAN := FALSE;--TRUE;
+  CONSTANT c_use_tx                  : BOOLEAN := TRUE;
+  CONSTANT c_tx_input_use_fifo       : BOOLEAN := TRUE;   -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+  CONSTANT c_tx_input_fifo_size      : NATURAL := c_bram_m9k_fifo_depth;   -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
+  CONSTANT c_tx_input_fifo_fill      : NATURAL := 0;
+  CONSTANT c_use_rx                  : BOOLEAN := TRUE;
+  CONSTANT c_rx_output_use_fifo      : BOOLEAN := TRUE;   -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+  CONSTANT c_rx_output_fifo_size     : NATURAL := c_bram_m9k_fifo_depth;   -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
+  CONSTANT c_rx_output_fifo_fill     : NATURAL := 128;
+  CONSTANT c_rx_timeout_w            : NATURAL := 0;      -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
+  CONSTANT c_mon_select              : NATURAL := 0;      
+  CONSTANT c_mon_nof_words           : NATURAL := 1024;
+  CONSTANT c_mon_use_sync            : BOOLEAN := TRUE;
+  CONSTANT c_uth_len_max             : NATURAL := 255;    -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+  CONSTANT c_uth_typ_ofs             : NATURAL := 256;    -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs
+  CONSTANT c_aux                     : t_c_unb1_board_aux := c_unb1_board_aux;
+  CONSTANT c_use_bsn_align           : BOOLEAN := TRUE;  -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis)
+  CONSTANT c_use_data_buf            : BOOLEAN := TRUE;
+                                     
+  CONSTANT c_mesh_mon_select         : NATURAL := 1;     -- > 0 = enable SOSI data buffers monitor via MM
+  CONSTANT c_mesh_mon_nof_words      : NATURAL := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size;  -- = 1024
+  CONSTANT c_mesh_mon_use_sync       : BOOLEAN := TRUE;  -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
+                                     
+  CONSTANT c_reg_diag_db_adr_w       : NATURAL := 5;
+
+  -- System
+  SIGNAL cs_sim                      : STD_LOGIC;
+  SIGNAL xo_clk                      : STD_LOGIC;
+  SIGNAL xo_rst                      : STD_LOGIC;
+  SIGNAL xo_rst_n                    : STD_LOGIC;
+  SIGNAL mm_clk                      : STD_LOGIC;
+  SIGNAL mm_locked                   : STD_LOGIC;
+  SIGNAL mm_rst                      : STD_LOGIC;
+  SIGNAL cal_clk                     : STD_LOGIC;
+  SIGNAL epcs_clk                    : STD_LOGIC; 
+                                     
+  SIGNAL dp_rst                      : STD_LOGIC;
+  SIGNAL dp_clk                      : STD_LOGIC;
+  SIGNAL dp_pps                      : STD_LOGIC;
+                                     
+  SIGNAL this_chip_id                : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);  -- [2:0], so range 0-3 for FN and range 4-7 BN
+                                     
+  -- PIOs                            
+  SIGNAL pout_debug_wave             : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL pout_wdi                    : STD_LOGIC;
+
+  -- WDI override
+  SIGNAL reg_wdi_mosi                : t_mem_mosi;
+  SIGNAL reg_wdi_miso                : t_mem_miso;
+
+  -- WDI override
+  SIGNAL reg_ppsh_mosi               : t_mem_mosi;
+  SIGNAL reg_ppsh_miso               : t_mem_miso;
+                                     
+  -- UniBoard system info            
+  SIGNAL reg_unb_system_info_mosi    : t_mem_mosi;
+  SIGNAL reg_unb_system_info_miso    : t_mem_miso;
+  SIGNAL rom_unb_system_info_mosi    : t_mem_mosi;
+  SIGNAL rom_unb_system_info_miso    : t_mem_miso;  
+                                     
+  -- UniBoard I2C sens               
+  SIGNAL reg_unb_sens_mosi           : t_mem_mosi;  -- mms_unb_sens registers
+  SIGNAL reg_unb_sens_miso           : t_mem_miso;
+                                     
+  -- eth1g                           
+  SIGNAL eth1g_tse_clk               : STD_LOGIC;
+  SIGNAL eth1g_mm_rst                : STD_LOGIC;
+  SIGNAL eth1g_tse_mosi              : t_mem_mosi := c_mem_mosi_rst;  -- ETH TSE MAC registers
+  SIGNAL eth1g_tse_miso              : t_mem_miso;
+  SIGNAL eth1g_reg_mosi              : t_mem_mosi := c_mem_mosi_rst;  -- ETH control and status registers
+  SIGNAL eth1g_reg_miso              : t_mem_miso;
+  SIGNAL eth1g_reg_interrupt         : STD_LOGIC;   -- Interrupt
+  SIGNAL eth1g_ram_mosi              : t_mem_mosi := c_mem_mosi_rst;  -- ETH rx frame and tx frame memory
+  SIGNAL eth1g_ram_miso              : t_mem_miso;
+
+  -- tr_mesh                         
+  SIGNAL tx_serial_2arr              : t_unb1_board_mesh_sl_2arr;    -- Tx
+  SIGNAL rx_serial_2arr              : t_unb1_board_mesh_sl_2arr;    -- Rx support for diagnostics
+    
+  -- MM tr_nonbonded with diagnostics
+  SIGNAL reg_tr_nonbonded_mosi       : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_tr_nonbonded_miso       : t_mem_miso;
+                                     
+  SIGNAL reg_diagnostics_mosi        : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_diagnostics_miso        : t_mem_miso;
+
+  -- MM diag_block_generator
+  SIGNAL ram_diag_bg_mosi            : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_diag_bg_miso            : t_mem_miso;
+  SIGNAL reg_diag_bg_mosi            : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_diag_bg_miso            : t_mem_miso;  
+                                     
+  -- MM diag_data_buffer real 
+  SIGNAL ram_diag_data_buf_re_mosi   : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_diag_data_buf_re_miso   : t_mem_miso;
+  SIGNAL reg_diag_data_buf_re_mosi   : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_diag_data_buf_re_miso   : t_mem_miso;  
+
+  -- MM diag_data_buffer imag 
+  SIGNAL ram_diag_data_buf_im_mosi   : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_diag_data_buf_im_miso   : t_mem_miso;
+  SIGNAL reg_diag_data_buf_im_mosi   : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_diag_data_buf_im_miso   : t_mem_miso;  
+
+  -- MM reorder_row blocks
+  SIGNAL ram_reorder_row_input_mosi  : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_reorder_row_input_miso  : t_mem_miso;
+  SIGNAL ram_reorder_row_mesh_mosi   : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_reorder_row_mesh_miso   : t_mem_miso;  
+
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- General control function
+  -----------------------------------------------------------------------------
+  u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+  GENERIC MAP (
+    g_sim             => g_sim,
+    g_design_name     => g_design_name,
+    g_design_note     => g_design_note,
+    g_stamp_date      => g_stamp_date,
+    g_stamp_time      => g_stamp_time, 
+    g_stamp_svn       => g_stamp_svn, 
+    g_fw_version      => c_fw_version,
+    g_sim_flash_model => NOT(g_sim),
+    g_mm_clk_freq     => c_unb1_board_mm_clk_freq_125M,
+    g_use_phy         => c_use_phy,
+    g_aux             => c_unb1_board_aux,
+    g_dp_clk_use_pll  => TRUE,
+    g_xo_clk_use_pll  => TRUE
+  )
+  PORT MAP (
+    -- Clock and reset signals
+    cs_sim                   => cs_sim,
+    xo_clk                   => xo_clk,
+    xo_rst                   => xo_rst,
+    xo_rst_n                 => xo_rst_n,
+
+    mm_clk_out               => mm_clk,
+    mm_clk                   => mm_clk,
+    mm_rst                   => mm_rst,
+
+    mm_locked                => mm_locked,
+    mm_locked_out            => mm_locked,
+
+    epcs_clk                 => epcs_clk,
+    epcs_clk_out             => epcs_clk,
+
+    dp_rst                   => dp_rst,
+    dp_clk                   => dp_clk,
+    dp_pps                   => dp_pps,
+    dp_rst_in                => dp_rst,
+    dp_clk_in                => dp_clk,
+
+    cal_rec_clk              => cal_clk,    
+    
+    this_chip_id             => this_chip_id,
+    
+    -- Toggle WDI
+    pout_wdi                 => pout_wdi,    
+
+    -- MM buses
+    -- . Manual WDI override
+    reg_wdi_mosi             => reg_wdi_mosi,
+    reg_wdi_miso             => reg_wdi_miso,
+    
+    -- . System_info
+    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso => reg_unb_system_info_miso, 
+    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso => rom_unb_system_info_miso, 
+    
+    -- . UniBoard I2C sensors
+    reg_unb_sens_mosi        => reg_unb_sens_mosi,
+    reg_unb_sens_miso        => reg_unb_sens_miso,    
+    
+    -- PPSH                                    
+    reg_ppsh_mosi            => reg_ppsh_mosi,     
+    reg_ppsh_miso            => reg_ppsh_miso,     
+
+    -- eth1g
+    -- eth1g
+    eth1g_tse_clk_out        => eth1g_tse_clk,
+    eth1g_tse_clk            => eth1g_tse_clk,
+    eth1g_mm_rst             => eth1g_mm_rst,
+    eth1g_tse_mosi           => eth1g_tse_mosi,
+    eth1g_tse_miso           => eth1g_tse_miso,
+    eth1g_reg_mosi           => eth1g_reg_mosi,
+    eth1g_reg_miso           => eth1g_reg_miso,
+    eth1g_reg_interrupt      => eth1g_reg_interrupt,
+    eth1g_ram_mosi           => eth1g_ram_mosi,
+    eth1g_ram_miso           => eth1g_ram_miso,
+
+    -- FPGA pins
+    -- . General
+    CLK                      => CLK,
+    PPS                      => PPS,
+    WDI                      => WDI,
+    INTA                     => INTA,
+    INTB                     => INTB,
+    -- . Others
+    VERSION                  => VERSION,
+    ID                       => ID,
+    TESTIO                   => TESTIO,
+    -- . I2C Interface to Sensors
+    sens_sc                  => sens_sc,
+    sens_sd                  => sens_sd,        
+    -- . 1GbE Control Interface
+    ETH_clk                  => ETH_clk,
+    ETH_SGIN                 => ETH_SGIN,
+    ETH_SGOUT                => ETH_SGOUT
+  );
+
+  -----------------------------------------------------------------------------
+  -- MM master
+  -----------------------------------------------------------------------------
+  u_inst_mmm_apertif_unb1_cor_mesh_ref : ENTITY work.mmm_apertif_unb1_cor_mesh_ref
+  GENERIC MAP(
+     g_sim         => g_sim,
+     g_sim_unb_nr  => g_sim_unb_nr,
+     g_sim_node_nr => g_sim_node_nr
+   )
+   PORT MAP(
+     mm_clk                     =>  mm_clk,
+     mm_rst                     =>  mm_rst,
+     pout_wdi                   =>  pout_wdi,
+     reg_wdi_mosi               =>  reg_wdi_mosi,
+     reg_wdi_miso               =>  reg_wdi_miso,
+     reg_unb_system_info_mosi   =>  reg_unb_system_info_mosi,
+     reg_unb_system_info_miso   =>  reg_unb_system_info_miso,
+     rom_unb_system_info_mosi   =>  rom_unb_system_info_mosi,
+     rom_unb_system_info_miso   =>  rom_unb_system_info_miso,
+     reg_unb_sens_mosi          =>  reg_unb_sens_mosi,
+     reg_unb_sens_miso          =>  reg_unb_sens_miso,
+     reg_ppsh_mosi              =>  reg_ppsh_mosi,
+     reg_ppsh_miso              =>  reg_ppsh_miso,
+     eth1g_mm_rst               =>  eth1g_mm_rst,
+     eth1g_reg_interrupt        =>  eth1g_reg_interrupt,
+     eth1g_ram_mosi             =>  eth1g_ram_mosi,
+     eth1g_ram_miso             =>  eth1g_ram_miso,
+     eth1g_reg_mosi             =>  eth1g_reg_mosi,
+     eth1g_reg_miso             =>  eth1g_reg_miso,
+     eth1g_tse_mosi             =>  eth1g_tse_mosi,
+     eth1g_tse_miso             =>  eth1g_tse_miso,
+     reg_diag_data_buf_re_mosi  =>  reg_diag_data_buf_re_mosi,
+     reg_diag_data_buf_re_miso  =>  reg_diag_data_buf_re_miso,
+     ram_diag_data_buf_re_mosi  =>  ram_diag_data_buf_re_mosi,
+     ram_diag_data_buf_re_miso  =>  ram_diag_data_buf_re_miso,
+     reg_diag_data_buf_im_mosi  =>  reg_diag_data_buf_im_mosi,
+     reg_diag_data_buf_im_miso  =>  reg_diag_data_buf_im_miso,
+     ram_diag_data_buf_im_mosi  =>  ram_diag_data_buf_im_mosi,
+     ram_diag_data_buf_im_miso  =>  ram_diag_data_buf_im_miso,
+     reg_diag_bg_mosi           =>  reg_diag_bg_mosi,
+     reg_diag_bg_miso           =>  reg_diag_bg_miso,
+     ram_diag_bg_mosi           =>  ram_diag_bg_mosi,
+     ram_diag_bg_miso           =>  ram_diag_bg_miso,
+     reg_diagnostics_mosi       =>  reg_diagnostics_mosi,
+     reg_diagnostics_miso       =>  reg_diagnostics_miso,
+     reg_tr_nonbonded_mosi      =>  reg_tr_nonbonded_mosi,
+     reg_tr_nonbonded_miso      =>  reg_tr_nonbonded_miso,
+     ram_reorder_row_input_mosi =>  ram_reorder_row_input_mosi,
+     ram_reorder_row_input_miso =>  ram_reorder_row_input_miso,
+     ram_reorder_row_mesh_mosi  =>  ram_reorder_row_mesh_mosi,
+     ram_reorder_row_mesh_miso  =>  ram_reorder_row_mesh_miso
+   );
+ 
+  -----------------------------------------------------------------------------
+  -- Node function: Terminals and data buffer
+  -----------------------------------------------------------------------------  
+  u_terminal_mesh : ENTITY work.node_apertif_unb1_cor_mesh_ref 
+  GENERIC MAP(
+    g_sim                     => g_sim,       
+    g_sim_level               => g_sim_level, 
+    g_sim_node_nr             => g_sim_node_nr,
+    
+    -- MESH TERMINAL
+    -- System
+    g_node_type               => c_node_type,           
+    g_nof_bus                 => c_nof_bus,             
+    -- User                                             
+    g_usr_use_complex         => c_usr_use_complex,     
+    g_usr_data_w              => c_usr_data_w,          
+    g_usr_frame_len           => c_usr_frame_len,       
+    g_usr_nof_streams         => c_usr_nof_streams,     
+    -- Phy                                              
+    g_phy_nof_serial          => c_phy_nof_serial,  
+    g_phy_gx_mbps             => c_phy_gx_mbps,     
+    g_phy_rx_fifo_size        => c_phy_rx_fifo_size,
+    g_phy_ena_reorder         => c_phy_ena_reorder,
+    -- Tx                                               
+    g_use_tx                  => c_use_tx,              
+    g_tx_input_use_fifo       => c_tx_input_use_fifo,   
+    g_tx_input_fifo_size      => c_tx_input_fifo_size,  
+    g_tx_input_fifo_fill      => c_tx_input_fifo_fill,  
+    -- Rx
+    g_use_rx                  => c_use_rx,              
+    g_rx_output_use_fifo      => c_rx_output_use_fifo,  
+    g_rx_output_fifo_size     => c_rx_output_fifo_size, 
+    g_rx_output_fifo_fill     => c_rx_output_fifo_fill, 
+    g_rx_timeout_w            => c_rx_timeout_w,        
+    -- Monitoring
+    g_mon_select              => c_mon_select,          
+    g_mon_nof_words           => c_mon_nof_words,       
+    g_mon_use_sync            => c_mon_use_sync,        
+    -- UTH
+    g_uth_len_max             => c_uth_len_max,         
+    g_uth_typ_ofs             => c_uth_typ_ofs,         
+
+    -- Auxiliary Interface
+    g_aux                     => c_unb1_board_aux
+  )
+  PORT MAP(
+    -- System
+    chip_id                     => this_chip_id,
+    mm_rst                      => mm_rst,
+    mm_clk                      => mm_clk,             
+    dp_rst                      => dp_rst,             
+    dp_clk                      => dp_clk,             
+    dp_pps                      => dp_pps,             
+    tr_mesh_clk                 => SB_CLK, 
+    cal_clk                     => cal_clk,             
+
+    -- MM interface
+    reg_diag_bg_mosi            => reg_diag_bg_mosi,
+    reg_diag_bg_miso            => reg_diag_bg_miso,
+    ram_diag_bg_mosi            => ram_diag_bg_mosi,
+    ram_diag_bg_miso            => ram_diag_bg_miso,
+    ram_diag_data_buf_re_mosi   => ram_diag_data_buf_re_mosi,
+    ram_diag_data_buf_re_miso   => ram_diag_data_buf_re_miso,
+    reg_diag_data_buf_re_mosi   => reg_diag_data_buf_re_mosi,
+    reg_diag_data_buf_re_miso   => reg_diag_data_buf_re_miso,
+    ram_diag_data_buf_im_mosi   => ram_diag_data_buf_im_mosi,
+    ram_diag_data_buf_im_miso   => ram_diag_data_buf_im_miso,
+    reg_diag_data_buf_im_mosi   => reg_diag_data_buf_im_mosi,
+    reg_diag_data_buf_im_miso   => reg_diag_data_buf_im_miso,
+    reg_tr_nonbonded_mosi       => reg_tr_nonbonded_mosi,      
+    reg_tr_nonbonded_miso       => reg_tr_nonbonded_miso,      
+    reg_diagnostics_mosi        => reg_diagnostics_mosi,       
+    reg_diagnostics_miso        => reg_diagnostics_miso, 
+    ram_reorder_row_input_mosi  => ram_reorder_row_input_mosi,
+    ram_reorder_row_input_miso  => ram_reorder_row_input_miso,
+    ram_reorder_row_mesh_mosi   => ram_reorder_row_mesh_mosi,
+    ram_reorder_row_mesh_miso   => ram_reorder_row_mesh_miso,
+
+    -- Mesh serial interface (tr_nonbonded)
+    tx_serial_2arr              => tx_serial_2arr, 
+    rx_serial_2arr              => rx_serial_2arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- Mesh I/O
+  -----------------------------------------------------------------------------  
+  no_tr_mesh : IF c_use_phy.tr_mesh=0 GENERATE
+    rx_serial_2arr <= (OTHERS=>(OTHERS=>'0'));
+  END GENERATE;
+  
+  gen_tr_mesh : IF c_use_phy.tr_mesh/=0 GENERATE
+    u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
+    GENERIC MAP (
+      g_bus_w => c_unb1_board_tr_mesh.bus_w
+    )
+    PORT MAP (
+      tx_serial_2arr => tx_serial_2arr,
+      rx_serial_2arr => rx_serial_2arr,
+      
+      -- Serial I/O
+      FN_BN_0_TX     => FN_BN_0_TX,
+      FN_BN_0_RX     => FN_BN_0_RX,
+      FN_BN_1_TX     => FN_BN_1_TX,
+      FN_BN_1_RX     => FN_BN_1_RX,
+      FN_BN_2_TX     => FN_BN_2_TX,
+      FN_BN_2_RX     => FN_BN_2_RX,
+      FN_BN_3_TX     => FN_BN_3_TX,
+      FN_BN_3_RX     => FN_BN_3_RX
+    );
+  END GENERATE;
+  
+END;
+
+
+
+
+
+
+
+
+
+
+
+