diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/apertif_unb1_cor_mesh_ref.vhd b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/apertif_unb1_cor_mesh_ref.vhd new file mode 100644 index 0000000000000000000000000000000000000000..4336ee736416e2b88efbe92a082867ffbf4938f6 --- /dev/null +++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/apertif_unb1_cor_mesh_ref.vhd @@ -0,0 +1,491 @@ +------------------------------------------------------------------------------ +-- +-- Copyright (C) 2011 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_network_layers_pkg.ALL; +USE common_lib.common_network_total_header_pkg.ALL; +USE unb1_board_lib.unb1_board_pkg.ALL; +USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE eth_lib.eth_pkg.ALL; +USE tech_tse_lib.tech_tse_pkg.ALL; +USE tech_tse_lib.tb_tech_tse_pkg.ALL; + +ENTITY apertif_unb1_cor_mesh_ref IS + GENERIC ( + -- General + g_design_name : STRING := "unb1_terminal_bg_mesh_db"; + g_design_note : STRING := "UNUSED"; + g_sim : BOOLEAN := FALSE; --Overridden by TB + g_sim_level : NATURAL := 0; + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF + g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF + g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF + ); + PORT ( + -- GENERAL + CLK : IN STD_LOGIC; -- System Clock + PPS : IN STD_LOGIC; -- System Sync + WDI : OUT STD_LOGIC; -- Watchdog Clear + INTA : INOUT STD_LOGIC; -- FPGA interconnect line + INTB : INOUT STD_LOGIC; -- FPGA interconnect line + + -- Others + VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0); + ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0); + TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0); + + -- I2C Interface to Sensors + sens_sc : INOUT STD_LOGIC; + sens_sd : INOUT STD_LOGIC; + + -- 1GbE Control Interface + ETH_clk : IN STD_LOGIC; + ETH_SGIN : IN STD_LOGIC; + ETH_SGOUT : OUT STD_LOGIC; + + -- Transceiver clocks + SB_CLK : IN STD_LOGIC := '0'; -- TR clock FN-BN (mesh) + + -- Serial I/O + FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); + FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); + FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); + FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); + FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); + FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); + FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0); + FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0') + ); +END apertif_unb1_cor_mesh_ref; + + +ARCHITECTURE str OF apertif_unb1_cor_mesh_ref IS + + CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1); + CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y + + CONSTANT c_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn + CONSTANT c_nof_bus : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh + CONSTANT c_usr_use_complex : BOOLEAN := TRUE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data + CONSTANT c_usr_data_w : NATURAL := 8; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit + CONSTANT c_usr_frame_len : NATURAL := 128; --20; + CONSTANT c_usr_nof_streams : NATURAL := 3; -- number of user streams per bus + CONSTANT c_phy_nof_serial : NATURAL := 3; -- up to 4 serial lanes per bus + CONSTANT c_phy_gx_mbps : NATURAL := 6250; --5000; + CONSTANT c_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY + CONSTANT c_phy_ena_reorder : BOOLEAN := FALSE;--TRUE; + CONSTANT c_use_tx : BOOLEAN := TRUE; + CONSTANT c_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers + CONSTANT c_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx + CONSTANT c_tx_input_fifo_fill : NATURAL := 0; + CONSTANT c_use_rx : BOOLEAN := TRUE; + CONSTANT c_rx_output_use_fifo : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output + CONSTANT c_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx + CONSTANT c_rx_output_fifo_fill : NATURAL := 128; + CONSTANT c_rx_timeout_w : NATURAL := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid + CONSTANT c_mon_select : NATURAL := 0; + CONSTANT c_mon_nof_words : NATURAL := 1024; + CONSTANT c_mon_use_sync : BOOLEAN := TRUE; + CONSTANT c_uth_len_max : NATURAL := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs + CONSTANT c_uth_typ_ofs : NATURAL := 256; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs + CONSTANT c_aux : t_c_unb1_board_aux := c_unb1_board_aux; + CONSTANT c_use_bsn_align : BOOLEAN := TRUE; -- default TRUE, support FALSE for packet flow debugging purposes (faster synthesis) + CONSTANT c_use_data_buf : BOOLEAN := TRUE; + + CONSTANT c_mesh_mon_select : NATURAL := 1; -- > 0 = enable SOSI data buffers monitor via MM + CONSTANT c_mesh_mon_nof_words : NATURAL := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size; -- = 1024 + CONSTANT c_mesh_mon_use_sync : BOOLEAN := TRUE; -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word + + CONSTANT c_reg_diag_db_adr_w : NATURAL := 5; + + -- System + SIGNAL cs_sim : STD_LOGIC; + SIGNAL xo_clk : STD_LOGIC; + SIGNAL xo_rst : STD_LOGIC; + SIGNAL xo_rst_n : STD_LOGIC; + SIGNAL mm_clk : STD_LOGIC; + SIGNAL mm_locked : STD_LOGIC; + SIGNAL mm_rst : STD_LOGIC; + SIGNAL cal_clk : STD_LOGIC; + SIGNAL epcs_clk : STD_LOGIC; + + SIGNAL dp_rst : STD_LOGIC; + SIGNAL dp_clk : STD_LOGIC; + SIGNAL dp_pps : STD_LOGIC; + + SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN + + -- PIOs + SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); + SIGNAL pout_wdi : STD_LOGIC; + + -- WDI override + SIGNAL reg_wdi_mosi : t_mem_mosi; + SIGNAL reg_wdi_miso : t_mem_miso; + + -- WDI override + SIGNAL reg_ppsh_mosi : t_mem_mosi; + SIGNAL reg_ppsh_miso : t_mem_miso; + + -- UniBoard system info + SIGNAL reg_unb_system_info_mosi : t_mem_mosi; + SIGNAL reg_unb_system_info_miso : t_mem_miso; + SIGNAL rom_unb_system_info_mosi : t_mem_mosi; + SIGNAL rom_unb_system_info_miso : t_mem_miso; + + -- UniBoard I2C sens + SIGNAL reg_unb_sens_mosi : t_mem_mosi; -- mms_unb_sens registers + SIGNAL reg_unb_sens_miso : t_mem_miso; + + -- eth1g + SIGNAL eth1g_tse_clk : STD_LOGIC; + SIGNAL eth1g_mm_rst : STD_LOGIC; + SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers + SIGNAL eth1g_tse_miso : t_mem_miso; + SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers + SIGNAL eth1g_reg_miso : t_mem_miso; + SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt + SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory + SIGNAL eth1g_ram_miso : t_mem_miso; + + -- tr_mesh + SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Tx + SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr; -- Rx support for diagnostics + + -- MM tr_nonbonded with diagnostics + SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_tr_nonbonded_miso : t_mem_miso; + + SIGNAL reg_diagnostics_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_diagnostics_miso : t_mem_miso; + + -- MM diag_block_generator + SIGNAL ram_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL ram_diag_bg_miso : t_mem_miso; + SIGNAL reg_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_diag_bg_miso : t_mem_miso; + + -- MM diag_data_buffer real + SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL ram_diag_data_buf_re_miso : t_mem_miso; + SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_diag_data_buf_re_miso : t_mem_miso; + + -- MM diag_data_buffer imag + SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL ram_diag_data_buf_im_miso : t_mem_miso; + SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL reg_diag_data_buf_im_miso : t_mem_miso; + + -- MM reorder_row blocks + SIGNAL ram_reorder_row_input_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL ram_reorder_row_input_miso : t_mem_miso; + SIGNAL ram_reorder_row_mesh_mosi : t_mem_mosi := c_mem_mosi_rst; + SIGNAL ram_reorder_row_mesh_miso : t_mem_miso; + + +BEGIN + + ----------------------------------------------------------------------------- + -- General control function + ----------------------------------------------------------------------------- + u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board + GENERIC MAP ( + g_sim => g_sim, + g_design_name => g_design_name, + g_design_note => g_design_note, + g_stamp_date => g_stamp_date, + g_stamp_time => g_stamp_time, + g_stamp_svn => g_stamp_svn, + g_fw_version => c_fw_version, + g_sim_flash_model => NOT(g_sim), + g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M, + g_use_phy => c_use_phy, + g_aux => c_unb1_board_aux, + g_dp_clk_use_pll => TRUE, + g_xo_clk_use_pll => TRUE + ) + PORT MAP ( + -- Clock and reset signals + cs_sim => cs_sim, + xo_clk => xo_clk, + xo_rst => xo_rst, + xo_rst_n => xo_rst_n, + + mm_clk_out => mm_clk, + mm_clk => mm_clk, + mm_rst => mm_rst, + + mm_locked => mm_locked, + mm_locked_out => mm_locked, + + epcs_clk => epcs_clk, + epcs_clk_out => epcs_clk, + + dp_rst => dp_rst, + dp_clk => dp_clk, + dp_pps => dp_pps, + dp_rst_in => dp_rst, + dp_clk_in => dp_clk, + + cal_rec_clk => cal_clk, + + this_chip_id => this_chip_id, + + -- Toggle WDI + pout_wdi => pout_wdi, + + -- MM buses + -- . Manual WDI override + reg_wdi_mosi => reg_wdi_mosi, + reg_wdi_miso => reg_wdi_miso, + + -- . System_info + reg_unb_system_info_mosi => reg_unb_system_info_mosi, + reg_unb_system_info_miso => reg_unb_system_info_miso, + rom_unb_system_info_mosi => rom_unb_system_info_mosi, + rom_unb_system_info_miso => rom_unb_system_info_miso, + + -- . UniBoard I2C sensors + reg_unb_sens_mosi => reg_unb_sens_mosi, + reg_unb_sens_miso => reg_unb_sens_miso, + + -- PPSH + reg_ppsh_mosi => reg_ppsh_mosi, + reg_ppsh_miso => reg_ppsh_miso, + + -- eth1g + -- eth1g + eth1g_tse_clk_out => eth1g_tse_clk, + eth1g_tse_clk => eth1g_tse_clk, + eth1g_mm_rst => eth1g_mm_rst, + eth1g_tse_mosi => eth1g_tse_mosi, + eth1g_tse_miso => eth1g_tse_miso, + eth1g_reg_mosi => eth1g_reg_mosi, + eth1g_reg_miso => eth1g_reg_miso, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_mosi, + eth1g_ram_miso => eth1g_ram_miso, + + -- FPGA pins + -- . General + CLK => CLK, + PPS => PPS, + WDI => WDI, + INTA => INTA, + INTB => INTB, + -- . Others + VERSION => VERSION, + ID => ID, + TESTIO => TESTIO, + -- . I2C Interface to Sensors + sens_sc => sens_sc, + sens_sd => sens_sd, + -- . 1GbE Control Interface + ETH_clk => ETH_clk, + ETH_SGIN => ETH_SGIN, + ETH_SGOUT => ETH_SGOUT + ); + + ----------------------------------------------------------------------------- + -- MM master + ----------------------------------------------------------------------------- + u_inst_mmm_apertif_unb1_cor_mesh_ref : ENTITY work.mmm_apertif_unb1_cor_mesh_ref + GENERIC MAP( + g_sim => g_sim, + g_sim_unb_nr => g_sim_unb_nr, + g_sim_node_nr => g_sim_node_nr + ) + PORT MAP( + mm_clk => mm_clk, + mm_rst => mm_rst, + pout_wdi => pout_wdi, + reg_wdi_mosi => reg_wdi_mosi, + reg_wdi_miso => reg_wdi_miso, + reg_unb_system_info_mosi => reg_unb_system_info_mosi, + reg_unb_system_info_miso => reg_unb_system_info_miso, + rom_unb_system_info_mosi => rom_unb_system_info_mosi, + rom_unb_system_info_miso => rom_unb_system_info_miso, + reg_unb_sens_mosi => reg_unb_sens_mosi, + reg_unb_sens_miso => reg_unb_sens_miso, + reg_ppsh_mosi => reg_ppsh_mosi, + reg_ppsh_miso => reg_ppsh_miso, + eth1g_mm_rst => eth1g_mm_rst, + eth1g_reg_interrupt => eth1g_reg_interrupt, + eth1g_ram_mosi => eth1g_ram_mosi, + eth1g_ram_miso => eth1g_ram_miso, + eth1g_reg_mosi => eth1g_reg_mosi, + eth1g_reg_miso => eth1g_reg_miso, + eth1g_tse_mosi => eth1g_tse_mosi, + eth1g_tse_miso => eth1g_tse_miso, + reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi, + reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso, + ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi, + ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso, + reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi, + reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso, + ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi, + ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso, + reg_diag_bg_mosi => reg_diag_bg_mosi, + reg_diag_bg_miso => reg_diag_bg_miso, + ram_diag_bg_mosi => ram_diag_bg_mosi, + ram_diag_bg_miso => ram_diag_bg_miso, + reg_diagnostics_mosi => reg_diagnostics_mosi, + reg_diagnostics_miso => reg_diagnostics_miso, + reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi, + reg_tr_nonbonded_miso => reg_tr_nonbonded_miso, + ram_reorder_row_input_mosi => ram_reorder_row_input_mosi, + ram_reorder_row_input_miso => ram_reorder_row_input_miso, + ram_reorder_row_mesh_mosi => ram_reorder_row_mesh_mosi, + ram_reorder_row_mesh_miso => ram_reorder_row_mesh_miso + ); + + ----------------------------------------------------------------------------- + -- Node function: Terminals and data buffer + ----------------------------------------------------------------------------- + u_terminal_mesh : ENTITY work.node_apertif_unb1_cor_mesh_ref + GENERIC MAP( + g_sim => g_sim, + g_sim_level => g_sim_level, + g_sim_node_nr => g_sim_node_nr, + + -- MESH TERMINAL + -- System + g_node_type => c_node_type, + g_nof_bus => c_nof_bus, + -- User + g_usr_use_complex => c_usr_use_complex, + g_usr_data_w => c_usr_data_w, + g_usr_frame_len => c_usr_frame_len, + g_usr_nof_streams => c_usr_nof_streams, + -- Phy + g_phy_nof_serial => c_phy_nof_serial, + g_phy_gx_mbps => c_phy_gx_mbps, + g_phy_rx_fifo_size => c_phy_rx_fifo_size, + g_phy_ena_reorder => c_phy_ena_reorder, + -- Tx + g_use_tx => c_use_tx, + g_tx_input_use_fifo => c_tx_input_use_fifo, + g_tx_input_fifo_size => c_tx_input_fifo_size, + g_tx_input_fifo_fill => c_tx_input_fifo_fill, + -- Rx + g_use_rx => c_use_rx, + g_rx_output_use_fifo => c_rx_output_use_fifo, + g_rx_output_fifo_size => c_rx_output_fifo_size, + g_rx_output_fifo_fill => c_rx_output_fifo_fill, + g_rx_timeout_w => c_rx_timeout_w, + -- Monitoring + g_mon_select => c_mon_select, + g_mon_nof_words => c_mon_nof_words, + g_mon_use_sync => c_mon_use_sync, + -- UTH + g_uth_len_max => c_uth_len_max, + g_uth_typ_ofs => c_uth_typ_ofs, + + -- Auxiliary Interface + g_aux => c_unb1_board_aux + ) + PORT MAP( + -- System + chip_id => this_chip_id, + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + dp_pps => dp_pps, + tr_mesh_clk => SB_CLK, + cal_clk => cal_clk, + + -- MM interface + reg_diag_bg_mosi => reg_diag_bg_mosi, + reg_diag_bg_miso => reg_diag_bg_miso, + ram_diag_bg_mosi => ram_diag_bg_mosi, + ram_diag_bg_miso => ram_diag_bg_miso, + ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi, + ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso, + reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi, + reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso, + ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi, + ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso, + reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi, + reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso, + reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi, + reg_tr_nonbonded_miso => reg_tr_nonbonded_miso, + reg_diagnostics_mosi => reg_diagnostics_mosi, + reg_diagnostics_miso => reg_diagnostics_miso, + ram_reorder_row_input_mosi => ram_reorder_row_input_mosi, + ram_reorder_row_input_miso => ram_reorder_row_input_miso, + ram_reorder_row_mesh_mosi => ram_reorder_row_mesh_mosi, + ram_reorder_row_mesh_miso => ram_reorder_row_mesh_miso, + + -- Mesh serial interface (tr_nonbonded) + tx_serial_2arr => tx_serial_2arr, + rx_serial_2arr => rx_serial_2arr + ); + + ----------------------------------------------------------------------------- + -- Mesh I/O + ----------------------------------------------------------------------------- + no_tr_mesh : IF c_use_phy.tr_mesh=0 GENERATE + rx_serial_2arr <= (OTHERS=>(OTHERS=>'0')); + END GENERATE; + + gen_tr_mesh : IF c_use_phy.tr_mesh/=0 GENERATE + u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io + GENERIC MAP ( + g_bus_w => c_unb1_board_tr_mesh.bus_w + ) + PORT MAP ( + tx_serial_2arr => tx_serial_2arr, + rx_serial_2arr => rx_serial_2arr, + + -- Serial I/O + FN_BN_0_TX => FN_BN_0_TX, + FN_BN_0_RX => FN_BN_0_RX, + FN_BN_1_TX => FN_BN_1_TX, + FN_BN_1_RX => FN_BN_1_RX, + FN_BN_2_TX => FN_BN_2_TX, + FN_BN_2_RX => FN_BN_2_RX, + FN_BN_3_TX => FN_BN_3_TX, + FN_BN_3_RX => FN_BN_3_RX + ); + END GENERATE; + +END; + + + + + + + + + + + + diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd new file mode 100644 index 0000000000000000000000000000000000000000..ec07c39e65656db096ec38d32f4164ea3251a682 --- /dev/null +++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd @@ -0,0 +1,491 @@ +-------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- + +-- u_inst_mmm_apertif_unb1_cor_mesh_ref : ENTITY work.mmm_apertif_unb1_cor_mesh_ref +-- GENERIC MAP( +-- g_sim => g_sim, +-- g_sim_unb_nr => g_sim_unb_nr, +-- g_sim_node_nr => g_sim_node_nr +-- ) +-- PORT MAP( +-- mm_clk => mm_clk, +-- mm_rst => mm_rst, +-- pout_wdi => pout_wdi, +-- reg_wdi_mosi => reg_wdi_mosi, +-- reg_wdi_miso => reg_wdi_miso, +-- reg_unb_system_info_mosi => reg_unb_system_info_mosi, +-- reg_unb_system_info_miso => reg_unb_system_info_miso, +-- rom_unb_system_info_mosi => rom_unb_system_info_mosi, +-- rom_unb_system_info_miso => rom_unb_system_info_miso, +-- reg_unb_sens_mosi => reg_unb_sens_mosi, +-- reg_unb_sens_miso => reg_unb_sens_miso, +-- reg_ppsh_mosi => reg_ppsh_mosi, +-- reg_ppsh_miso => reg_ppsh_miso, +-- eth1g_mm_rst => eth1g_mm_rst, +-- eth1g_reg_interrupt => eth1g_reg_interrupt, +-- eth1g_ram_mosi => eth1g_ram_mosi, +-- eth1g_ram_miso => eth1g_ram_miso, +-- eth1g_reg_mosi => eth1g_reg_mosi, +-- eth1g_reg_miso => eth1g_reg_miso, +-- eth1g_tse_mosi => eth1g_tse_mosi, +-- eth1g_tse_miso => eth1g_tse_miso, +-- reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi, +-- reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso, +-- ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi, +-- ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso, +-- reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi, +-- reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso, +-- ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi, +-- ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso, +-- reg_diag_bg_mosi => reg_diag_bg_mosi, +-- reg_diag_bg_miso => reg_diag_bg_miso, +-- ram_diag_bg_mosi => ram_diag_bg_mosi, +-- ram_diag_bg_miso => ram_diag_bg_miso, +-- reg_diagnostics_mosi => reg_diagnostics_mosi, +-- reg_diagnostics_miso => reg_diagnostics_miso, +-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi, +-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso, +-- ram_reorder_row_input_mosi => ram_reorder_row_input_mosi, +-- ram_reorder_row_input_miso => ram_reorder_row_input_miso, +-- ram_reorder_row_mesh_mosi => ram_reorder_row_mesh_mosi, +-- ram_reorder_row_mesh_miso => ram_reorder_row_mesh_miso +-- ); +-- +LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.tb_common_mem_pkg.ALL; +USE common_lib.common_field_pkg.ALL; +USE common_lib.common_network_total_header_pkg.ALL; +USE common_lib.common_network_layers_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE unb1_board_lib.unb1_board_pkg.ALL; +USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; +USE mm_lib.mm_file_pkg.ALL; +USE mm_lib.mm_file_unb_pkg.ALL; +USE eth_lib.eth_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE tech_tse_lib.tech_tse_pkg.ALL; +USE tech_tse_lib.tb_tech_tse_pkg.ALL; + +ENTITY mmm_apertif_unb1_cor_mesh_ref IS + GENERIC ( + g_sim : BOOLEAN := FALSE; + g_sim_unb_nr : NATURAL := 0; + g_sim_node_nr : NATURAL := 0 + ); + PORT ( + mm_clk : IN STD_LOGIC := '1'; + mm_rst : IN STD_LOGIC := '1'; + pout_wdi : OUT STD_LOGIC := '1'; + reg_wdi_mosi : OUT t_mem_mosi; + reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst; + reg_unb_system_info_mosi : OUT t_mem_mosi; + reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst; + rom_unb_system_info_mosi : OUT t_mem_mosi; + rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst; + reg_unb_sens_mosi : OUT t_mem_mosi; + reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst; + reg_ppsh_mosi : OUT t_mem_mosi; + reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst; + eth1g_mm_rst : OUT STD_LOGIC; + eth1g_reg_interrupt : IN STD_LOGIC; + eth1g_ram_mosi : OUT t_mem_mosi; + eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst; + eth1g_reg_mosi : OUT t_mem_mosi; + eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst; + eth1g_tse_mosi : OUT t_mem_mosi; + eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst; + reg_diag_data_buf_re_mosi : OUT t_mem_mosi; + reg_diag_data_buf_re_miso : IN t_mem_miso := c_mem_miso_rst; + ram_diag_data_buf_re_mosi : OUT t_mem_mosi; + ram_diag_data_buf_re_miso : IN t_mem_miso := c_mem_miso_rst; + reg_diag_data_buf_im_mosi : OUT t_mem_mosi; + reg_diag_data_buf_im_miso : IN t_mem_miso := c_mem_miso_rst; + ram_diag_data_buf_im_mosi : OUT t_mem_mosi; + ram_diag_data_buf_im_miso : IN t_mem_miso := c_mem_miso_rst; + reg_diag_bg_mosi : OUT t_mem_mosi; + reg_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst; + ram_diag_bg_mosi : OUT t_mem_mosi; + ram_diag_bg_miso : IN t_mem_miso := c_mem_miso_rst; + reg_diagnostics_mosi : OUT t_mem_mosi; + reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst; + reg_tr_nonbonded_mosi : OUT t_mem_mosi; + reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst; + ram_reorder_row_input_mosi : OUT t_mem_mosi; + ram_reorder_row_input_miso : IN t_mem_miso := c_mem_miso_rst; + ram_reorder_row_mesh_mosi : OUT t_mem_mosi; + ram_reorder_row_mesh_miso : IN t_mem_miso := c_mem_miso_rst + ); +END ENTITY mmm_apertif_unb1_cor_mesh_ref; + +ARCHITECTURE str OF mmm_apertif_unb1_cor_mesh_ref IS + + CONSTANT c_sim_node_type : STRING(1 TO 2) := sel_a_b(g_sim_node_nr<4, "FN", "BN"); + CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr); + CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w); + CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en; + + SIGNAL sim_eth_mm_bus_switch : STD_LOGIC ; + SIGNAL sim_eth_psc_access : STD_LOGIC ; + SIGNAL i_eth1g_reg_mosi : t_mem_mosi; + SIGNAL i_eth1g_reg_miso : t_mem_miso; + SIGNAL mm_rst_n : STD_LOGIC ; + SIGNAL sim_eth1g_reg_mosi : t_mem_mosi; + + COMPONENT mm_file IS + GENERIC ( + g_file_prefix : STRING ; + g_mm_clk_period : TIME := 8 ns; + g_update_on_change : BOOLEAN := FALSE; + g_mm_rd_latency : NATURAL := 1 + ); + PORT ( + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; + mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst; + mm_master_in : IN t_mem_miso := c_mem_miso_rst + ); + END COMPONENT mm_file; + + COMPONENT qsys_apertif_unb1_cor_mesh_ref IS + PORT ( + reg_diag_bg_reset_export : out std_logic; + ram_diag_bg_read_export : out std_logic; + eth1g_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_diagnostics_write_export : out std_logic; + reset_in_reset_n : in std_logic := '0'; + ram_diag_data_buf_im_read_export : out std_logic; + pio_system_info_address_export : out std_logic_vector(4 downto 0); + pio_pps_address_export : out std_logic; + pio_pps_reset_export : out std_logic; + eth1g_tse_writedata_export : out std_logic_vector(31 downto 0); + eth1g_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + eth1g_ram_address_export : out std_logic_vector(9 downto 0); + pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); + pio_system_info_writedata_export : out std_logic_vector(31 downto 0); + eth1g_reg_writedata_export : out std_logic_vector(31 downto 0); + reg_unb_sens_reset_export : out std_logic; + eth1g_tse_address_export : out std_logic_vector(9 downto 0); + reg_wdi_reset_export : out std_logic; + clk_in_clk : in std_logic := '0'; + ram_diag_data_buf_im_reset_export : out std_logic; + rom_system_info_clk_export : out std_logic; + reg_unb_sens_read_export : out std_logic; + reg_unb_sens_write_export : out std_logic; + reg_diag_data_buf_im_write_export : out std_logic; + ram_diag_bg_reset_export : out std_logic; + eth1g_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + eth1g_ram_write_export : out std_logic; + reg_diagnostics_writedata_export : out std_logic_vector(31 downto 0); + reg_diag_data_buf_re_reset_export : out std_logic; + reg_tr_nonbonded_clk_export : out std_logic; + reg_unb_sens_clk_export : out std_logic; + reg_diag_data_buf_re_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + ram_diag_data_buf_re_clk_export : out std_logic; + reg_diag_data_buf_im_reset_export : out std_logic; + reg_diag_data_buf_re_read_export : out std_logic; + reg_diag_data_buf_re_write_export : out std_logic; + ram_diag_data_buf_re_reset_export : out std_logic; + ram_diag_bg_write_export : out std_logic; + ram_diag_bg_address_export : out std_logic_vector(9 downto 0); + reg_diag_data_buf_im_writedata_export : out std_logic_vector(31 downto 0); + reg_wdi_read_export : out std_logic; + eth1g_ram_read_export : out std_logic; + ram_diag_data_buf_re_writedata_export : out std_logic_vector(31 downto 0); + eth1g_reg_read_export : out std_logic; + ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); + reg_diag_data_buf_re_writedata_export : out std_logic_vector(31 downto 0); + reg_diag_data_buf_re_address_export : out std_logic; + eth1g_tse_write_export : out std_logic; + ram_diag_data_buf_re_address_export : out std_logic_vector(9 downto 0); + reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + pio_pps_clk_export : out std_logic; + ram_diag_data_buf_re_read_export : out std_logic; + eth1g_reg_address_export : out std_logic_vector(3 downto 0); + ram_diag_data_buf_re_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_diag_bg_address_export : out std_logic_vector(2 downto 0); + pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + ram_diag_data_buf_im_address_export : out std_logic_vector(9 downto 0); + rom_system_info_writedata_export : out std_logic_vector(31 downto 0); + reg_tr_nonbonded_reset_export : out std_logic; + ram_diag_data_buf_im_writedata_export : out std_logic_vector(31 downto 0); + reg_tr_nonbonded_address_export : out std_logic_vector(3 downto 0); + reg_wdi_address_export : out std_logic; + reg_diag_bg_clk_export : out std_logic; + ram_diag_data_buf_im_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + pio_system_info_write_export : out std_logic; + pio_pps_write_export : out std_logic; + reg_tr_nonbonded_write_export : out std_logic; + reg_tr_nonbonded_writedata_export : out std_logic_vector(31 downto 0); + rom_system_info_write_export : out std_logic; + rom_system_info_read_export : out std_logic; + reg_diagnostics_address_export : out std_logic_vector(5 downto 0); + reg_tr_nonbonded_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_diag_bg_read_export : out std_logic; + eth1g_tse_read_export : out std_logic; + reg_diag_data_buf_im_read_export : out std_logic; + ram_diag_data_buf_im_clk_export : out std_logic; + ram_diag_bg_clk_export : out std_logic; + reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); + eth1g_ram_writedata_export : out std_logic_vector(31 downto 0); + reg_tr_nonbonded_read_export : out std_logic; + out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); + ram_diag_data_buf_re_write_export : out std_logic; + pio_system_info_reset_export : out std_logic; + reg_wdi_writedata_export : out std_logic_vector(31 downto 0); + pio_system_info_read_export : out std_logic; + reg_diag_data_buf_im_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_wdi_clk_export : out std_logic; + reg_diag_bg_write_export : out std_logic; + ram_diag_data_buf_im_write_export : out std_logic; + reg_diag_data_buf_im_address_export : out std_logic; + eth1g_mm_rst_export : out std_logic; + reg_diagnostics_read_export : out std_logic; + reg_diagnostics_reset_export : out std_logic; + out_port_from_the_pio_wdi : out std_logic; + eth1g_reg_write_export : out std_logic; + reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_wdi_write_export : out std_logic; + reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + pio_pps_read_export : out std_logic; + reg_diag_data_buf_im_clk_export : out std_logic; + pio_system_info_clk_export : out std_logic; + eth1g_tse_waitrequest_export : in std_logic := '0'; + pio_pps_writedata_export : out std_logic_vector(31 downto 0); + eth1g_mm_clk_export : out std_logic; + rom_system_info_reset_export : out std_logic; + reg_unb_sens_address_export : out std_logic_vector(2 downto 0); + rom_system_info_address_export : out std_logic_vector(9 downto 0); + reg_diag_data_buf_re_clk_export : out std_logic; + eth1g_irq_export : in std_logic := '0'; + reg_diagnostics_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); + reg_diagnostics_clk_export : out std_logic + ); + END COMPONENT qsys_apertif_unb1_cor_mesh_ref; + + +BEGIN + + ---------------------------------------------------------------------------- + -- MM <-> file I/O for simulation. The files are created in $UPE/sim. + ---------------------------------------------------------------------------- + gen_mm_file_io : IF g_sim = TRUE GENERATE + u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI") + PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso ); + u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO") + PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso ); + u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO") + PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso ); + u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS") + PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso ); + u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS") + PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso ); + u_mm_file_eth1g_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM") + PORT MAP(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso ); + u_mm_file_eth1g_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG") + PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso ); + u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE") + PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso ); + u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_RE") + PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso ); + u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_RE") + PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso ); + u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_IM") + PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso ); + u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_IM") + PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso ); + u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG") + PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso ); + u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG") + PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso ); + u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS") + PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso ); + u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED") + PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso ); + u_mm_file_ram_reorder_row_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_REORDER_ROW_INPUT") + PORT MAP(mm_rst, mm_clk, ram_reorder_row_input_mosi, ram_reorder_row_input_miso ); + u_mm_file_ram_reorder_row_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_REORDER_ROW_MESH") + PORT MAP(mm_rst, mm_clk, ram_reorder_row_mesh_mosi, ram_reorder_row_mesh_miso ); + ---------------------------------------------------------------------------- + -- 1GbE setup sequence normally performed by unb_os@NIOS + ---------------------------------------------------------------------------- + p_eth_setup : PROCESS + BEGIN + sim_eth_mm_bus_switch <= '1'; + eth1g_tse_mosi.wr <= '0'; + eth1g_tse_mosi.rd <= '0'; + WAIT FOR 400 ns; + WAIT UNTIL rising_edge(mm_clk); + proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi); + -- Enable RX + proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en + sim_eth_mm_bus_switch <= '0'; + WAIT; + END PROCESS; + + p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi) + BEGIN + IF sim_eth_mm_bus_switch = '1' THEN + eth1g_reg_mosi <= sim_eth1g_reg_mosi; + ELSE + eth1g_reg_mosi <= i_eth1g_reg_mosi; + END IF; + END PROCESS; + ---------------------------------------------------------------------------- + -- Procedure that polls a sim control file that can be used to e.g. get + -- the simulation time in ns + ---------------------------------------------------------------------------- + mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat"); + + END GENERATE; + ---------------------------------------------------------------------------- + -- SOPC or QSYS for synthesis + ---------------------------------------------------------------------------- + gen_qsys_apertif_unb1_cor_mesh_ref : IF g_sim = FALSE GENERATE + + mm_rst_n <= NOT(mm_rst); + + u_qsys_apertif_unb1_cor_mesh_ref : qsys_apertif_unb1_cor_mesh_ref + PORT MAP( + clk_in_clk => mm_clk, + eth1g_irq_export => eth1g_reg_interrupt, + eth1g_mm_clk_export => OPEN, + eth1g_mm_rst_export => eth1g_mm_rst, + eth1g_ram_address_export => eth1g_ram_mosi.address(9 DOWNTO 0), + eth1g_ram_read_export => eth1g_ram_mosi.rd, + eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0), + eth1g_ram_write_export => eth1g_ram_mosi.wr, + eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0), + eth1g_reg_address_export => eth1g_reg_mosi.address(3 DOWNTO 0), + eth1g_reg_read_export => eth1g_reg_mosi.rd, + eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0), + eth1g_reg_write_export => eth1g_reg_mosi.wr, + eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0), + eth1g_tse_address_export => eth1g_tse_mosi.address(9 DOWNTO 0), + eth1g_tse_read_export => eth1g_tse_mosi.rd, + eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0), + eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest, + eth1g_tse_write_export => eth1g_tse_mosi.wr, + eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0), + out_port_from_the_pio_debug_wave => OPEN, + out_port_from_the_pio_wdi => pout_wdi, + pio_pps_address_export => reg_ppsh_mosi.address(0), + pio_pps_clk_export => OPEN, + pio_pps_read_export => reg_ppsh_mosi.rd, + pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0), + pio_pps_reset_export => OPEN, + pio_pps_write_export => reg_ppsh_mosi.wr, + pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0), + pio_system_info_address_export => reg_unb_system_info_mosi.address(4 DOWNTO 0), + pio_system_info_clk_export => OPEN, + pio_system_info_read_export => reg_unb_system_info_mosi.rd, + pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), + pio_system_info_reset_export => OPEN, + pio_system_info_write_export => reg_unb_system_info_mosi.wr, + pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0), + ram_diag_bg_address_export => ram_diag_bg_mosi.address(9 DOWNTO 0), + ram_diag_bg_clk_export => OPEN, + ram_diag_bg_read_export => ram_diag_bg_mosi.rd, + ram_diag_bg_readdata_export => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0), + ram_diag_bg_reset_export => OPEN, + ram_diag_bg_write_export => ram_diag_bg_mosi.wr, + ram_diag_bg_writedata_export => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0), + ram_diag_data_buf_im_address_export => ram_diag_data_buf_im_mosi.address(9 DOWNTO 0), + ram_diag_data_buf_im_clk_export => OPEN, + ram_diag_data_buf_im_read_export => ram_diag_data_buf_im_mosi.rd, + ram_diag_data_buf_im_readdata_export => ram_diag_data_buf_im_miso.rddata(c_word_w-1 DOWNTO 0), + ram_diag_data_buf_im_reset_export => OPEN, + ram_diag_data_buf_im_write_export => ram_diag_data_buf_im_mosi.wr, + ram_diag_data_buf_im_writedata_export => ram_diag_data_buf_im_mosi.wrdata(c_word_w-1 DOWNTO 0), + ram_diag_data_buf_re_address_export => ram_diag_data_buf_re_mosi.address(9 DOWNTO 0), + ram_diag_data_buf_re_clk_export => OPEN, + ram_diag_data_buf_re_read_export => ram_diag_data_buf_re_mosi.rd, + ram_diag_data_buf_re_readdata_export => ram_diag_data_buf_re_miso.rddata(c_word_w-1 DOWNTO 0), + ram_diag_data_buf_re_reset_export => OPEN, + ram_diag_data_buf_re_write_export => ram_diag_data_buf_re_mosi.wr, + ram_diag_data_buf_re_writedata_export => ram_diag_data_buf_re_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_diag_bg_address_export => reg_diag_bg_mosi.address(2 DOWNTO 0), + reg_diag_bg_clk_export => OPEN, + reg_diag_bg_read_export => reg_diag_bg_mosi.rd, + reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0), + reg_diag_bg_reset_export => OPEN, + reg_diag_bg_write_export => reg_diag_bg_mosi.wr, + reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_diag_data_buf_im_address_export => reg_diag_data_buf_im_mosi.address(0), + reg_diag_data_buf_im_clk_export => OPEN, + reg_diag_data_buf_im_read_export => reg_diag_data_buf_im_mosi.rd, + reg_diag_data_buf_im_readdata_export => reg_diag_data_buf_im_miso.rddata(c_word_w-1 DOWNTO 0), + reg_diag_data_buf_im_reset_export => OPEN, + reg_diag_data_buf_im_write_export => reg_diag_data_buf_im_mosi.wr, + reg_diag_data_buf_im_writedata_export => reg_diag_data_buf_im_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_diag_data_buf_re_address_export => reg_diag_data_buf_re_mosi.address(0), + reg_diag_data_buf_re_clk_export => OPEN, + reg_diag_data_buf_re_read_export => reg_diag_data_buf_re_mosi.rd, + reg_diag_data_buf_re_readdata_export => reg_diag_data_buf_re_miso.rddata(c_word_w-1 DOWNTO 0), + reg_diag_data_buf_re_reset_export => OPEN, + reg_diag_data_buf_re_write_export => reg_diag_data_buf_re_mosi.wr, + reg_diag_data_buf_re_writedata_export => reg_diag_data_buf_re_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_diagnostics_address_export => reg_diagnostics_mosi.address(5 DOWNTO 0), + reg_diagnostics_clk_export => OPEN, + reg_diagnostics_read_export => reg_diagnostics_mosi.rd, + reg_diagnostics_readdata_export => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0), + reg_diagnostics_reset_export => OPEN, + reg_diagnostics_write_export => reg_diagnostics_mosi.wr, + reg_diagnostics_writedata_export => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_tr_nonbonded_address_export => reg_tr_nonbonded_mosi.address(3 DOWNTO 0), + reg_tr_nonbonded_clk_export => OPEN, + reg_tr_nonbonded_read_export => reg_tr_nonbonded_mosi.rd, + reg_tr_nonbonded_readdata_export => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0), + reg_tr_nonbonded_reset_export => OPEN, + reg_tr_nonbonded_write_export => reg_tr_nonbonded_mosi.wr, + reg_tr_nonbonded_writedata_export => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 DOWNTO 0), + reg_unb_sens_clk_export => OPEN, + reg_unb_sens_read_export => reg_unb_sens_mosi.rd, + reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0), + reg_unb_sens_reset_export => OPEN, + reg_unb_sens_write_export => reg_unb_sens_mosi.wr, + reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0), + reg_wdi_address_export => reg_wdi_mosi.address(0), + reg_wdi_clk_export => OPEN, + reg_wdi_read_export => reg_wdi_mosi.rd, + reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0), + reg_wdi_reset_export => OPEN, + reg_wdi_write_export => reg_wdi_mosi.wr, + reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0), + reset_in_reset_n => mm_rst_n, + rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0), + rom_system_info_clk_export => OPEN, + rom_system_info_read_export => rom_unb_system_info_mosi.rd, + rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0), + rom_system_info_reset_export => OPEN, + rom_system_info_write_export => rom_unb_system_info_mosi.wr, + rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0) + ); + END GENERATE; + +END str; diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/node_apertif_unb1_cor_mesh_ref.vhd b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/node_apertif_unb1_cor_mesh_ref.vhd new file mode 100644 index 0000000000000000000000000000000000000000..176260a5e851124394690a0ba2fa85fd3da05aed --- /dev/null +++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/node_apertif_unb1_cor_mesh_ref.vhd @@ -0,0 +1,482 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: +-- +-- Description: +-- +-- Remarks: +-- +-- +-- Some more remarks: + +LIBRARY IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, apertif_lib, reorder_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE unb1_board_lib.unb1_board_pkg.ALL; +USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; +USE diag_lib.diag_pkg.ALL; +USE reorder_lib.reorder_pkg.ALL; + +ENTITY node_apertif_unb1_cor_mesh_ref IS + GENERIC( + g_sim : BOOLEAN := FALSE; + g_sim_level : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + + -- MESH TERMINAL + -- System + g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn + g_nof_bus : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh + -- User + g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data + g_usr_data_w : NATURAL := 16; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit + g_usr_frame_len : NATURAL := 20; + g_usr_nof_streams : NATURAL := 3; -- number of user streams per bus + -- Phy + g_phy_nof_serial : NATURAL := 3; -- up to 4 serial lanes per bus + g_phy_gx_mbps : NATURAL := 5000; + g_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY + g_phy_ena_reorder : BOOLEAN := TRUE; + -- Tx + g_use_tx : BOOLEAN := TRUE; + g_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers + g_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx + g_tx_input_fifo_fill : NATURAL := 0; + -- Rx + g_use_rx : BOOLEAN := TRUE; + g_rx_output_use_fifo : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output + g_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx + g_rx_output_fifo_fill : NATURAL := 0; + g_rx_timeout_w : NATURAL := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid + -- Monitoring + g_mon_select : NATURAL := 0; -- 0 = no SOSI data buffers monitor via MM + -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded + -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder + -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx + -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute + -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded + -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder + g_mon_nof_words : NATURAL := 1024; + g_mon_use_sync : BOOLEAN := TRUE; + -- UTH + g_uth_len_max : NATURAL := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs + g_uth_typ_ofs : NATURAL := 256; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs + + -- Auxiliary Interface + g_aux : t_c_unb1_board_aux := c_unb1_board_aux + ); + PORT( + -- System + chip_id : IN STD_LOGIC_VECTOR(g_aux.chip_id_w-1 DOWNTO 0); -- [2:0] + + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; -- 50 MHz from xo_clk PLL in SOPC system + dp_rst : IN STD_LOGIC; + dp_clk : IN STD_LOGIC; -- 200 MHz from CLK system clock + dp_pps : IN STD_LOGIC := '0'; + tr_mesh_clk : IN STD_LOGIC; -- 156.25 MHz from SB_CLK transceiver clock + cal_clk : IN STD_LOGIC; -- 40 MHz from xo_clk PLL in SOPC system + + -- MM interface + -- . block generator + reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diag_bg_miso : OUT t_mem_miso; + ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_diag_bg_miso : OUT t_mem_miso; + -- . diag_data_buffer real + ram_diag_data_buf_re_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_diag_data_buf_re_miso : OUT t_mem_miso; + reg_diag_data_buf_re_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diag_data_buf_re_miso : OUT t_mem_miso; + -- . diag_data_buffer imag + ram_diag_data_buf_im_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_diag_data_buf_im_miso : OUT t_mem_miso; + reg_diag_data_buf_im_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diag_data_buf_im_miso : OUT t_mem_miso; + -- . tr_nonbonded + reg_tr_nonbonded_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_tr_nonbonded_miso : OUT t_mem_miso; + reg_diagnostics_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diagnostics_miso : OUT t_mem_miso; + -- . diag_data_buffer_mesh + ram_mesh_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_mesh_diag_data_buf_miso : OUT t_mem_miso; + -- . bsn_monitor + reg_bsn_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_bsn_monitor_miso : OUT t_mem_miso; + --. reorder input + ram_reorder_row_input_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_reorder_row_input_miso : OUT t_mem_miso; + --. reorder mesh + ram_reorder_row_mesh_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_reorder_row_mesh_miso : OUT t_mem_miso; + -- Mesh serial interface (tr_nonbonded) + tx_serial_2arr : OUT t_unb1_board_mesh_sl_2arr; -- Tx + rx_serial_2arr : IN t_unb1_board_mesh_sl_2arr:= (OTHERS=>(OTHERS=>'0')) -- Rx support for diagnostics + ); +END node_apertif_unb1_cor_mesh_ref; + +ARCHITECTURE str OF node_apertif_unb1_cor_mesh_ref IS + + CONSTANT c_sel_apertif_cor: t_sel_table := + ( + --FN0 FN1 FN2 FN3 BN0 BN1 BN2 BN3 + ( 0 , 10, 13, 16, 8 , 8 , 8 , 8 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 0 + ( 10, 2 , 16, 19, 11, 11, 11, 11, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 1 + ( 13, 16, 4 , 10, 14, 14, 14, 14, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 2 + ( 16, 19, 10, 6 , 17, 17, 17, 17, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 3 + ( 8 , 8 , 8 , 8 , 1 , 19, 16, 13, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 4 + ( 11, 11, 11, 11, 13, 3 , 19, 16, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 5 + ( 14, 14, 14, 14, 16, 13, 5 , 19, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 6 + ( 17, 17, 17, 17, 19, 16, 13, 7 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 7 + ( 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 0 + ( 2 , 0 , 6 , 4 , 20, 20, 20, 20, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 1 + ( 20, 12, 15, 18, 12, 15, 18, 20, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 2 + ( 3 , 3 , 3 , 3 , 2 , 2 , 2 , 2 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 3 + ( 4 , 20, 0 , 20, 7 , 1 , 3 , 5 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 4 + ( 20, 15, 18, 9, 9 , 20, 15, 18, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 5 + ( 5 , 5 , 5 , 5 , 4 , 4 , 4 , 4 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 6 + ( 6 , 4 , 2 , 0 , 5 , 7 , 1 , 3 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 7 + ( 20, 18, 9 , 12, 18, 9 , 12, 20, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 8 + ( 7 , 7 , 7 , 7 , 6 , 6 , 6 , 6 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 9 + ( 20, 6 , 20, 2 , 3 , 5 , 7 , 1 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 10 + ( 20, 9 , 12, 15, 15, 20, 9 , 12, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 11 + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) + ); + ----------------------------------------------------------------------------- + -- Block Generator + ----------------------------------------------------------------------------- + CONSTANT c_use_usr_input : BOOLEAN := FALSE; + CONSTANT c_bg_nof_streams : NATURAL := 8; + CONSTANT c_in_dat_w : NATURAL := g_usr_data_w; + CONSTANT c_bg_addr_w : NATURAL := 7; +-- CONSTANT c_node_nr : NATURAL := TO_UINT(chip_id); + CONSTANT c_file_name_prefix : STRING := "hex/node" & NATURAL'IMAGE(g_sim_node_nr) & "/bg_in_data"; + + ----------------------------------------------------------------------------- + -- Mesh Row Reorder + ----------------------------------------------------------------------------- + CONSTANT c_mesh_nof_streams : NATURAL := g_nof_bus * g_usr_nof_streams; -- 4x3=12 + + ----------------------------------------------------------------------------- + -- BSN Aligner + ----------------------------------------------------------------------------- + CONSTANT c_bsn_align_nof_streams : NATURAL := c_mesh_nof_streams; + CONSTANT c_block_size : NATURAL := 128; --FIXME: current fn_beamformer output block size. + CONSTANT c_block_period : NATURAL := 192; + CONSTANT c_bsn_align_latency : NATURAL := 3; + CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed + CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods + + ----------------------------------------------------------------------------- + -- BSN Monitor + ----------------------------------------------------------------------------- + CONSTANT c_bsn_mon_nof_streams : NATURAL := 1; + CONSTANT c_bsn_sync_time_out : NATURAL := (800000*256*10)/8; + + CONSTANT c_distr_nof_input_streams : NATURAL := c_bg_nof_streams + c_mesh_nof_streams + 1; + CONSTANT c_distr_nof_output_streams : NATURAL := c_bg_nof_streams + c_mesh_nof_streams; + + ----------------------------------------------------------------------------- + -- Data Buffer + ----------------------------------------------------------------------------- + CONSTANT c_db_nof_streams : NATURAL := c_bg_nof_streams; + CONSTANT c_db_nof_data : NATURAL := 128; + CONSTANT c_db_data_w : NATURAL := g_usr_data_w; + CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real; + CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag; + + --. Block generator + SIGNAL bg_snk_out_arr : t_dp_siso_arr(c_bg_nof_streams-1 DOWNTO 0); + SIGNAL bg_snk_in_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + SIGNAL bg_src_in_arr : t_dp_siso_arr(c_bg_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL bg_src_out_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + + --. Input reorder + SIGNAL local_mesh_tx_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + + --. Mesh reorder + SIGNAL mesh_reordered_rx_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + + -- 1d arrays for the mesh + SIGNAL rx_mesh_sosi_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + SIGNAL rx_mesh_siso_arr : t_dp_siso_arr(c_mesh_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL tx_mesh_sosi_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + SIGNAL tx_mesh_siso_arr : t_dp_siso_arr(c_mesh_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + + --. BSN Aligner + SIGNAL bsn_align_snk_in_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + SIGNAL bsn_align_snk_out_arr : t_dp_siso_arr(c_mesh_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL bsn_align_src_in_arr : t_dp_siso_arr(c_mesh_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL bsn_align_src_out_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + + --. Rewire + SIGNAL distr_input_sosi_arr : t_dp_sosi_arr(c_distr_nof_input_streams-1 DOWNTO 0); + SIGNAL distr_input_siso_arr : t_dp_siso_arr(c_distr_nof_input_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL distr_output_sosi_arr : t_dp_sosi_arr(c_distr_nof_output_streams-1 DOWNTO 0); + SIGNAL distr_output_siso_arr : t_dp_siso_arr(c_distr_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + + --. Mesh terminal + SIGNAL tx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr; + SIGNAL tx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr; + SIGNAL rx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr; + SIGNAL rx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr; + + --. Databuffer + SIGNAL db_snk_in_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + SIGNAL db_snk_out_arr : t_dp_siso_arr(c_bg_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + +BEGIN + + --------------------------------------------------------------------------------------- + -- Block Generator + --------------------------------------------------------------------------------------- + u_bg : ENTITY diag_lib.mms_diag_block_gen + GENERIC MAP( + -- Generate configurations + g_use_usr_input => c_use_usr_input, + g_use_bg => TRUE, + g_use_tx_seq => FALSE, + -- General + g_nof_streams => c_bg_nof_streams, + -- BG settings + g_use_bg_buffer_ram => TRUE, + g_buf_dat_w => c_nof_complex*c_in_dat_w, + g_buf_addr_w => c_bg_addr_w, + g_file_name_prefix => c_file_name_prefix, + -- User input multiplexer option + g_usr_bypass_xonoff => FALSE + ) + PORT MAP( + -- System + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + en_sync => dp_pps, + -- MM interface + reg_bg_ctrl_mosi => reg_diag_bg_mosi, + reg_bg_ctrl_miso => reg_diag_bg_miso, + ram_bg_data_mosi => ram_diag_bg_mosi, + ram_bg_data_miso => ram_diag_bg_miso, + + -- ST interface + usr_siso_arr => bg_snk_out_arr, + usr_sosi_arr => bg_snk_in_arr, + out_siso_arr => bg_src_in_arr, + out_sosi_arr => bg_src_out_arr + ); + + --------------------------------------------------------------------------------------- + -- From 2d to 1d array. Receiver part of the Mesh. + --------------------------------------------------------------------------------------- + gen_i_rx : FOR I IN 0 TO g_nof_bus-1 GENERATE + gen_j_rx : FOR J IN 0 TO g_usr_nof_streams-1 GENERATE + rx_mesh_sosi_arr(I*g_usr_nof_streams + J) <= rx_usr_sosi_2arr(I)(J); + rx_usr_siso_2arr(I)(J) <= rx_mesh_siso_arr(I*g_usr_nof_streams + J); + END GENERATE; + END GENERATE; + + --------------------------------------------------------------------------------------- + -- From 1d to 2d array. Transmitter part of the Mesh. + --------------------------------------------------------------------------------------- + gen_i_tx : FOR I IN 0 TO g_nof_bus-1 GENERATE + gen_j_tx : FOR J IN 0 TO g_usr_nof_streams-1 GENERATE + tx_usr_sosi_2arr(I)(J) <= tx_mesh_sosi_arr(I*g_usr_nof_streams + J); + tx_mesh_siso_arr(I*g_usr_nof_streams + J) <= tx_usr_siso_2arr(I)(J); + END GENERATE; + END GENERATE; + + --------------------------------------------------------------------------------------- + -- Concatenate inputs + --------------------------------------------------------------------------------------- + distr_input_sosi_arr(c_bg_nof_streams-1 DOWNTO 0) <= bg_src_out_arr; + distr_input_sosi_arr(c_bg_nof_streams + c_mesh_nof_streams-1 DOWNTO c_bg_nof_streams) <= rx_mesh_sosi_arr; + distr_input_sosi_arr(c_bg_nof_streams + c_mesh_nof_streams) <= c_dp_sosi_rst; + + bg_src_in_arr <= distr_input_siso_arr(c_bg_nof_streams-1 DOWNTO 0); + rx_mesh_siso_arr <= distr_input_siso_arr(c_bg_nof_streams + c_mesh_nof_streams-1 DOWNTO c_bg_nof_streams); + + u_rewire : ENTITY reorder_lib.reorder_rewire + GENERIC MAP( + g_select_table => c_sel_apertif_cor, + g_nof_configs => 8, + g_nof_input_streams => c_distr_nof_input_streams, + g_nof_output_streams => c_distr_nof_output_streams, + g_sel_in_w => 3 + ) + PORT MAP( + -- System + sel_in => chip_id, + input_sosi_arr => distr_input_sosi_arr, + input_siso_arr => distr_input_siso_arr, + output_sosi_arr => distr_output_sosi_arr, + output_siso_arr => distr_output_siso_arr + ); + + db_snk_in_arr <= distr_output_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + tx_mesh_sosi_arr <= distr_output_sosi_arr(c_bg_nof_streams + c_mesh_nof_streams-1 DOWNTO c_bg_nof_streams); + + distr_output_siso_arr(c_bg_nof_streams-1 DOWNTO 0) <= db_snk_out_arr; + distr_output_siso_arr(c_bg_nof_streams + c_mesh_nof_streams-1 DOWNTO c_bg_nof_streams) <= tx_mesh_siso_arr; + + u_mesh_terminal : ENTITY unb1_board_lib.unb1_board_terminals_mesh + GENERIC MAP( + g_sim => g_sim, + g_sim_level => g_sim_level, + -- System + g_node_type => g_node_type, + g_nof_bus => g_nof_bus, + -- User + g_usr_use_complex => g_usr_use_complex, + g_usr_data_w => g_usr_data_w, + g_usr_frame_len => g_usr_frame_len, + g_usr_nof_streams => g_usr_nof_streams, + -- Phy + g_phy_nof_serial => g_phy_nof_serial, + g_phy_gx_mbps => g_phy_gx_mbps, + g_phy_rx_fifo_size => g_phy_rx_fifo_size, + g_phy_ena_reorder => g_phy_ena_reorder, + -- Tx + g_use_tx => g_use_tx, + g_tx_input_use_fifo => g_tx_input_use_fifo, + g_tx_input_fifo_size => g_tx_input_fifo_size, + g_tx_input_fifo_fill => g_tx_input_fifo_fill, + -- Rx + g_use_rx => g_use_rx, + g_rx_output_use_fifo => g_rx_output_use_fifo, + g_rx_output_fifo_size => g_rx_output_fifo_size, + g_rx_output_fifo_fill => g_rx_output_fifo_fill, + g_rx_timeout_w => g_rx_timeout_w, + + -- Monitoring + g_mon_select => g_mon_select, + g_mon_nof_words => g_mon_nof_words, + g_mon_use_sync => g_mon_use_sync, + + -- UTH + g_uth_len_max => g_uth_len_max, + g_uth_typ_ofs => g_uth_typ_ofs + ) + PORT MAP ( + chip_id => chip_id, + + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + dp_sync => dp_pps, + tr_clk => tr_mesh_clk, + cal_clk => cal_clk, + + -- User interface (4 nodes)(4 input streams) + tx_usr_siso_2arr => tx_usr_siso_2arr, + tx_usr_sosi_2arr => tx_usr_sosi_2arr, -- <== Data to the Mesh + rx_usr_siso_2arr => rx_usr_siso_2arr, + rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- ==> Data from the Mesh + + -- Serial (tr_nonbonded) + tx_serial_2arr => tx_serial_2arr, + rx_serial_2arr => rx_serial_2arr, + + -- MM Control + -- . tr_nonbonded + reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi, + reg_tr_nonbonded_miso => reg_tr_nonbonded_miso, + reg_diagnostics_mosi => reg_diagnostics_mosi, + reg_diagnostics_miso => reg_diagnostics_miso, + + -- . monitor data buffer + ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi, + ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso + ); + + ---------------------------------------------------------------------------- + -- Sink: data buffer real + ---------------------------------------------------------------------------- + u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer + GENERIC MAP ( + g_nof_streams => c_db_nof_streams, + g_data_type => c_db_data_type_re, + g_data_w => c_db_data_w, + g_buf_nof_data => c_db_nof_data, + g_buf_use_sync => TRUE + ) + PORT MAP ( + -- System + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + -- MM interface + ram_data_buf_mosi => ram_diag_data_buf_re_mosi, + ram_data_buf_miso => ram_diag_data_buf_re_miso, + reg_data_buf_mosi => reg_diag_data_buf_re_mosi, + reg_data_buf_miso => reg_diag_data_buf_re_miso, + -- ST interface + in_sync => db_snk_in_arr(0).sync, + in_sosi_arr => db_snk_in_arr + ); + + ---------------------------------------------------------------------------- + -- Sink: data buffer imag + ---------------------------------------------------------------------------- + u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer + GENERIC MAP ( + g_nof_streams => c_db_nof_streams, + g_data_type => c_db_data_type_im, + g_data_w => c_db_data_w, + g_buf_nof_data => c_db_nof_data, + g_buf_use_sync => TRUE + ) + PORT MAP ( + -- System + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + -- MM interface + ram_data_buf_mosi => ram_diag_data_buf_im_mosi, + ram_data_buf_miso => ram_diag_data_buf_im_miso, + reg_data_buf_mosi => reg_diag_data_buf_im_mosi, + reg_data_buf_miso => reg_diag_data_buf_im_miso, + -- ST interface + in_sync => db_snk_in_arr(0).sync, + in_sosi_arr => db_snk_in_arr + ); + + +END str; diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/node_apertif_unb1_cor_mesh_ref_reorder_row.vhd b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/node_apertif_unb1_cor_mesh_ref_reorder_row.vhd new file mode 100644 index 0000000000000000000000000000000000000000..7a85c5a3952a1cdd5171f665754a8433dee4eeae --- /dev/null +++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/node_apertif_unb1_cor_mesh_ref_reorder_row.vhd @@ -0,0 +1,587 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: +-- +-- Description: +-- +-- Remarks: +-- +-- +-- Some more remarks: + +LIBRARY IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, apertif_lib, reorder_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE unb1_board_lib.unb1_board_pkg.ALL; +USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; +USE diag_lib.diag_pkg.ALL; + +ENTITY node_apertif_unb1_cor_mesh_ref IS + GENERIC( + g_sim : BOOLEAN := FALSE; + g_sim_level : NATURAL := 0; + g_sim_node_nr : NATURAL := 0; + + -- MESH TERMINAL + -- System + g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn + g_nof_bus : NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh + -- User + g_usr_use_complex : BOOLEAN := FALSE; -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data + g_usr_data_w : NATURAL := 16; -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit + g_usr_frame_len : NATURAL := 20; + g_usr_nof_streams : NATURAL := 3; -- number of user streams per bus + -- Phy + g_phy_nof_serial : NATURAL := 3; -- up to 4 serial lanes per bus + g_phy_gx_mbps : NATURAL := 5000; + g_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_fifos=TRUE in mms_tr_nonbonded, choose to use full BRAM size = 256 for FIFO depth at output from PHY + g_phy_ena_reorder : BOOLEAN := TRUE; + -- Tx + g_use_tx : BOOLEAN := TRUE; + g_tx_input_use_fifo : BOOLEAN := TRUE; -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers + g_tx_input_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx + g_tx_input_fifo_fill : NATURAL := 0; + -- Rx + g_use_rx : BOOLEAN := TRUE; + g_rx_output_use_fifo : BOOLEAN := TRUE; -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output + g_rx_output_fifo_size : NATURAL := c_bram_m9k_fifo_depth; -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx + g_rx_output_fifo_fill : NATURAL := 0; + g_rx_timeout_w : NATURAL := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid + -- Monitoring + g_mon_select : NATURAL := 0; -- 0 = no SOSI data buffers monitor via MM + -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded + -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder + -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx + -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute + -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded + -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder + g_mon_nof_words : NATURAL := 1024; + g_mon_use_sync : BOOLEAN := TRUE; + -- UTH + g_uth_len_max : NATURAL := 255; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs + g_uth_typ_ofs : NATURAL := 256; -- uth_rx g_uth_len_max < uth_tx g_uth_typ_ofs + + -- Auxiliary Interface + g_aux : t_c_unb1_board_aux := c_unb1_board_aux + ); + PORT( + -- System + chip_id : IN STD_LOGIC_VECTOR(g_aux.chip_id_w-1 DOWNTO 0); -- [2:0] + + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; -- 50 MHz from xo_clk PLL in SOPC system + dp_rst : IN STD_LOGIC; + dp_clk : IN STD_LOGIC; -- 200 MHz from CLK system clock + dp_pps : IN STD_LOGIC := '0'; + tr_mesh_clk : IN STD_LOGIC; -- 156.25 MHz from SB_CLK transceiver clock + cal_clk : IN STD_LOGIC; -- 40 MHz from xo_clk PLL in SOPC system + + -- MM interface + -- . block generator + reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diag_bg_miso : OUT t_mem_miso; + ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_diag_bg_miso : OUT t_mem_miso; + -- . diag_data_buffer real + ram_diag_data_buf_re_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_diag_data_buf_re_miso : OUT t_mem_miso; + reg_diag_data_buf_re_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diag_data_buf_re_miso : OUT t_mem_miso; + -- . diag_data_buffer imag + ram_diag_data_buf_im_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_diag_data_buf_im_miso : OUT t_mem_miso; + reg_diag_data_buf_im_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diag_data_buf_im_miso : OUT t_mem_miso; + -- . tr_nonbonded + reg_tr_nonbonded_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_tr_nonbonded_miso : OUT t_mem_miso; + reg_diagnostics_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_diagnostics_miso : OUT t_mem_miso; + -- . diag_data_buffer_mesh + ram_mesh_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_mesh_diag_data_buf_miso : OUT t_mem_miso; + -- . bsn_monitor + reg_bsn_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_bsn_monitor_miso : OUT t_mem_miso; + --. reorder input + ram_reorder_row_input_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_reorder_row_input_miso : OUT t_mem_miso; + --. reorder mesh + ram_reorder_row_mesh_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ram_reorder_row_mesh_miso : OUT t_mem_miso; + -- Mesh serial interface (tr_nonbonded) + tx_serial_2arr : OUT t_unb1_board_mesh_sl_2arr; -- Tx + rx_serial_2arr : IN t_unb1_board_mesh_sl_2arr:= (OTHERS=>(OTHERS=>'0')) -- Rx support for diagnostics + ); +END node_apertif_unb1_cor_mesh_ref; + +ARCHITECTURE str OF node_apertif_unb1_cor_mesh_ref IS + + ----------------------------------------------------------------------------- + -- Block Generator + ----------------------------------------------------------------------------- + CONSTANT c_use_usr_input : BOOLEAN := FALSE; + CONSTANT c_bg_nof_streams : NATURAL := 8; + CONSTANT c_in_dat_w : NATURAL := g_usr_data_w; + CONSTANT c_bg_addr_w : NATURAL := 7; +-- CONSTANT c_node_nr : NATURAL := TO_UINT(chip_id); + CONSTANT c_file_name_prefix : STRING := "hex/node" & NATURAL'IMAGE(g_sim_node_nr) & "/bg_in_data"; + + ----------------------------------------------------------------------------- + -- Mesh Row Reorder + ----------------------------------------------------------------------------- + CONSTANT c_mesh_nof_streams : NATURAL := g_nof_bus * g_usr_nof_streams; -- 4x3=12 + + ----------------------------------------------------------------------------- + -- BSN Aligner + ----------------------------------------------------------------------------- + CONSTANT c_bsn_align_nof_streams : NATURAL := c_mesh_nof_streams; + CONSTANT c_block_size : NATURAL := 128; --FIXME: current fn_beamformer output block size. + CONSTANT c_block_period : NATURAL := 192; + CONSTANT c_bsn_align_latency : NATURAL := 3; + CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed + CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods + + ----------------------------------------------------------------------------- + -- BSN Monitor + ----------------------------------------------------------------------------- + CONSTANT c_bsn_mon_nof_streams : NATURAL := 1; + CONSTANT c_bsn_sync_time_out : NATURAL := (800000*256*10)/8; + + ----------------------------------------------------------------------------- + -- Data Buffer + ----------------------------------------------------------------------------- + CONSTANT c_db_nof_streams : NATURAL := c_bg_nof_streams; + CONSTANT c_db_nof_data : NATURAL := 128; + CONSTANT c_db_data_w : NATURAL := g_usr_data_w; + CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real; + CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag; + + --. Block generator + SIGNAL bg_snk_out_arr : t_dp_siso_arr(c_bg_nof_streams-1 DOWNTO 0); + SIGNAL bg_snk_in_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + SIGNAL bg_src_in_arr : t_dp_siso_arr(c_bg_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL bg_src_out_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + + --. Input reorder + SIGNAL local_mesh_tx_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + + --. Mesh reorder + SIGNAL mesh_reordered_rx_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + + --. BSN Aligner + SIGNAL bsn_align_snk_in_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + SIGNAL bsn_align_snk_out_arr : t_dp_siso_arr(c_mesh_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL bsn_align_src_in_arr : t_dp_siso_arr(c_mesh_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL bsn_align_src_out_arr : t_dp_sosi_arr(c_mesh_nof_streams-1 DOWNTO 0); + + --. Mesh terminal + SIGNAL tx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr; + SIGNAL tx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr; + SIGNAL rx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr; + SIGNAL rx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr; + + --. Databuffer + SIGNAL db_snk_in_arr : t_dp_sosi_arr(c_bg_nof_streams-1 DOWNTO 0); + SIGNAL db_snk_out_arr : t_dp_siso_arr(c_bg_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + +BEGIN + + --------------------------------------------------------------------------------------- + -- Block Generator + --------------------------------------------------------------------------------------- + u_bg : ENTITY diag_lib.mms_diag_block_gen + GENERIC MAP( + -- Generate configurations + g_use_usr_input => c_use_usr_input, + g_use_bg => TRUE, + g_use_tx_seq => FALSE, + -- General + g_nof_streams => c_bg_nof_streams, + -- BG settings + g_use_bg_buffer_ram => TRUE, + g_buf_dat_w => c_nof_complex*c_in_dat_w, + g_buf_addr_w => c_bg_addr_w, + g_file_name_prefix => c_file_name_prefix, + -- User input multiplexer option + g_usr_bypass_xonoff => FALSE + ) + PORT MAP( + -- System + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + en_sync => dp_pps, + -- MM interface + reg_bg_ctrl_mosi => reg_diag_bg_mosi, + reg_bg_ctrl_miso => reg_diag_bg_miso, + ram_bg_data_mosi => ram_diag_bg_mosi, + ram_bg_data_miso => ram_diag_bg_miso, + + -- ST interface + usr_siso_arr => bg_snk_out_arr, + usr_sosi_arr => bg_snk_in_arr, + out_siso_arr => bg_src_in_arr, + out_sosi_arr => bg_src_out_arr + ); + + ----------------------------------------------------------- + -- Mapping for the reorder stage behind the input + -- The numbers define which input should be routed + -- to the output. Each row represesnt an output. + ----------------------------------------------------------- + -- Output FN 0, BN 0, FN 1, BN 1, FN 2, BN 2, FN 3, BN 3, + -- 0 1 0 1 0 1 0 1 0 + -- 1 0 1 2 1 4 7 6 5 + -- 2 3 2 3 2 3 2 3 2 + -- 3 6 5 0 3 2 1 4 7 + -- 4 5 4 5 4 5 4 5 4 + -- 5 4 7 6 5 0 3 2 1 + -- 6 7 6 7 6 7 6 7 6 + -- 7 2 1 4 7 6 5 0 3 + -- + -- FN 0: + -- 0101 1110 0101 1100 1100 0001 + -- 5 E 5 C C 1 = 0x5E5CC1 + -- + -- BN 0: + -- 0011 1011 1100 1010 1000 1000 + -- 3 B C A 8 8 = 0x3BCA88 + -- + -- FN 1: + -- 10011 111 0101 0000 1101 0001 + -- + + u_input_reorder : ENTITY reorder_lib.reorder_row + GENERIC MAP ( + g_dsp_data_w => g_usr_data_w, -- : NATURAL := 16; + g_frame_size => 1, --g_usr_frame_len, -- : NATURAL := 256; + g_nof_inputs => c_bg_nof_streams, -- : NATURAL := 8; + g_nof_outputs => c_bg_nof_streams, -- : NATURAL := 16; + g_ram_init_file => "UNUSED", -- : STRING := "../../../src/data/select_buf"; -- or "UNUSED" + g_pipeline_in => 1, -- : NATURAL := 1; -- pipeline in_data + g_pipeline_in_m => 1, -- : NATURAL := 1; -- pipeline in_data for M-fold fan out + g_pipeline_out => 1 -- : NATURAL := 1 -- pipeline out_data + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + + -- Memory Mapped + ram_ss_reorder_mosi => ram_reorder_row_input_mosi, + ram_ss_reorder_miso => ram_reorder_row_input_miso, + + -- Streaming + input_sosi_arr => bg_src_out_arr, + output_sosi_arr => local_mesh_tx_arr, + output_siso_arr => OPEN + ); + + u_mesh_I_reorder : ENTITY reorder_lib.reorder_row + GENERIC MAP ( + g_dsp_data_w => g_usr_data_w, -- : NATURAL := 16; + g_frame_size => 1, --g_usr_frame_len, -- : NATURAL := 256; + g_nof_inputs => 8, --c_mesh_nof_streams, -- : NATURAL := 8; + g_nof_outputs => 8, --c_mesh_nof_streams, -- : NATURAL := 16; + g_ram_init_file => "UNUSED", -- : STRING := "../../../src/data/select_buf"; -- or "UNUSED" + g_pipeline_in => 1, -- : NATURAL := 1; -- pipeline in_data + g_pipeline_in_m => 1, -- : NATURAL := 1; -- pipeline in_data for M-fold fan out + g_pipeline_out => 1 -- : NATURAL := 1 -- pipeline out_data + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + + -- Memory Mapped + ram_ss_reorder_mosi => ram_reorder_row_mesh_I_mosi, + ram_ss_reorder_miso => ram_reorder_row_mesh_I_miso, + + -- Streaming + input_sosi_arr => bsn_align_I_src_out_arr, + output_sosi_arr => mesh_reordered_rx_arr, + output_siso_arr => OPEN + ); + + u_mesh_II_reorder : ENTITY reorder_lib.reorder_row + GENERIC MAP ( + g_dsp_data_w => g_usr_data_w, -- : NATURAL := 16; + g_frame_size => 1, --g_usr_frame_len, -- : NATURAL := 256; + g_nof_inputs => 4, --c_mesh_nof_streams, -- : NATURAL := 8; + g_nof_outputs => 4, --c_mesh_nof_streams, -- : NATURAL := 16; + g_ram_init_file => "UNUSED", -- : STRING := "../../../src/data/select_buf"; -- or "UNUSED" + g_pipeline_in => 1, -- : NATURAL := 1; -- pipeline in_data + g_pipeline_in_m => 1, -- : NATURAL := 1; -- pipeline in_data for M-fold fan out + g_pipeline_out => 1 -- : NATURAL := 1 -- pipeline out_data + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + + -- Memory Mapped + ram_ss_reorder_mosi => ram_reorder_row_mesh_II_mosi, + ram_ss_reorder_miso => ram_reorder_row_mesh_II_miso, + + -- Streaming + input_sosi_arr => bsn_align_II_src_out_arr, + output_sosi_arr => mesh_reordered_rx_arr, + output_siso_arr => OPEN + ); + + --------------------------------------------------------------------------------------- + -- From 2d to 1d array. Receiver part of the Mesh. + --------------------------------------------------------------------------------------- + gen_i_rx : FOR I IN 0 TO g_nof_bus-1 GENERATE + gen_j_rx : FOR J IN 0 TO g_usr_nof_streams-1 GENERATE + bsn_align_snk_in_arr(I*g_usr_nof_streams + J) <= rx_usr_sosi_2arr(I)(J); + rx_usr_siso_2arr(I)(J) <= bsn_align_snk_out_arr(I*g_usr_nof_streams + J); + END GENERATE; + END GENERATE; + + + ----------------------------------------------------------------------------- + -- BSN ALIGNER I for 8 streams that are processed locally + ----------------------------------------------------------------------------- + u_dp_bsn_align : ENTITY dp_lib.dp_bsn_align + GENERIC MAP ( + g_block_size => c_block_size, + g_block_period => c_block_period, + g_nof_input => 8, + g_xoff_timeout => c_bsn_align_xoff_timeout, + g_sop_timeout => c_bsn_align_sop_timeout, + g_bsn_latency => c_bsn_align_latency, + g_bsn_request_pipeline => 2 + ) + PORT MAP ( + rst => dp_rst, + clk => dp_clk, + + snk_out_arr => bsn_align_I_snk_out_arr, + snk_in_arr => bsn_align_I_snk_in_arr, + + src_in_arr => bsn_align_I_src_in_arr, + src_out_arr => bsn_align_I_src_out_arr + ); + +----------------------------------------------------------------------------- + -- BSN ALIGNER II for 4 streams that are sent to Mesh TX + ----------------------------------------------------------------------------- + u_dp_bsn_align : ENTITY dp_lib.dp_bsn_align + GENERIC MAP ( + g_block_size => c_block_size, + g_block_period => c_block_period, + g_nof_input => 4, + g_xoff_timeout => c_bsn_align_xoff_timeout, + g_sop_timeout => c_bsn_align_sop_timeout, + g_bsn_latency => c_bsn_align_latency, + g_bsn_request_pipeline => 2 + ) + PORT MAP ( + rst => dp_rst, + clk => dp_clk, + + snk_out_arr => bsn_align_II_snk_out_arr, + snk_in_arr => bsn_align_II_snk_in_arr, + + src_in_arr => bsn_align_II_src_in_arr, + src_out_arr => bsn_align_II_src_out_arr + ); + + + --------------------------------------------------------------------------------------- + -- From 1d to 2d array. Transmitter part of the Mesh. + --------------------------------------------------------------------------------------- + gen_i_tx : FOR I IN 0 TO g_nof_bus-1 GENERATE + gen_j_tx : FOR J IN 0 TO g_usr_nof_streams-2 GENERATE + tx_usr_sosi_2arr(I)(J) <= local_mesh_tx_arr(I*(g_usr_nof_streams-1) + J); + END GENERATE; + tx_usr_sosi_2arr(I)(2) <= mesh_reordered_rx_arr(c_bg_nof_streams + I); + END GENERATE; + + db_snk_in_arr <= mesh_reordered_rx_arr(c_bg_nof_streams-1 DOWNTO 0); + + + u_distr: ENTITY apertif_lib.apertif_cor_mesh_distr + GENERIC MAP( + g_sim_node_nr => g_sim_node_nr, + g_aux => g_aux, --: t_c_unb1_board_aux := c_unb1_board_aux; + g_nof_bus => g_nof_bus, --: NATURAL := 4; -- one bus to each of the 4 nodes on the other side of the mesh + g_usr_nof_streams => g_usr_nof_streams, --: NATURAL := 3; -- number of user streams per bus + g_nof_input_streams => c_bg_nof_streams --: NATURAL := 8 + ) + PORT MAP( + -- System + chip_id => chip_id, --: IN STD_LOGIC_VECTOR(g_aux.chip_id_w-1 DOWNTO 0); -- [2:0] + + -- Inputs from transceiver + input_sosi_arr => bg_src_out_arr, -- : IN t_dp_sosi_arr(g_nof_input_streams-1 DOWNTO 0); + input_siso_arr => bg_src_in_arr, -- : OUT t_dp_siso_arr(g_nof_input_streams-1 DOWNTO 0); + + -- Outputs to processing + output_sosi_arr => db_snk_in_arr, --: IN t_dp_sosi_arr(g_nof_input_streams-1 DOWNTO 0); + output_siso_arr => db_snk_out_arr, --: OUT t_dp_siso_arr(g_nof_input_streams-1 DOWNTO 0); + + -- Mesh Transmit Interface + tx_mesh_siso_2arr => tx_usr_siso_2arr, --: IN t_unb1_board_mesh_siso_2arr := (OTHERS=>(OTHERS=>c_dp_siso_rdy)); + tx_mesh_sosi_2arr => tx_usr_sosi_2arr, --: OUT t_unb1_board_mesh_sosi_2arr; + + -- Mesh Receive Interface + rx_mesh_siso_2arr => rx_usr_siso_2arr, --: OUT t_unb1_board_mesh_siso_2arr; + rx_mesh_sosi_2arr => rx_usr_sosi_2arr --: IN t_unb1_board_mesh_sosi_2arr := (OTHERS=>(OTHERS=>c_dp_sosi_rst)) + ); + + u_mesh_terminal : ENTITY unb1_board_lib.unb1_board_terminals_mesh + GENERIC MAP( + g_sim => g_sim, + g_sim_level => g_sim_level, + -- System + g_node_type => g_node_type, + g_nof_bus => g_nof_bus, + -- User + g_usr_use_complex => g_usr_use_complex, + g_usr_data_w => g_usr_data_w, + g_usr_frame_len => g_usr_frame_len, + g_usr_nof_streams => g_usr_nof_streams, + -- Phy + g_phy_nof_serial => g_phy_nof_serial, + g_phy_gx_mbps => g_phy_gx_mbps, + g_phy_rx_fifo_size => g_phy_rx_fifo_size, + g_phy_ena_reorder => g_phy_ena_reorder, + -- Tx + g_use_tx => g_use_tx, + g_tx_input_use_fifo => g_tx_input_use_fifo, + g_tx_input_fifo_size => g_tx_input_fifo_size, + g_tx_input_fifo_fill => g_tx_input_fifo_fill, + -- Rx + g_use_rx => g_use_rx, + g_rx_output_use_fifo => g_rx_output_use_fifo, + g_rx_output_fifo_size => g_rx_output_fifo_size, + g_rx_output_fifo_fill => g_rx_output_fifo_fill, + g_rx_timeout_w => g_rx_timeout_w, + + -- Monitoring + g_mon_select => g_mon_select, + g_mon_nof_words => g_mon_nof_words, + g_mon_use_sync => g_mon_use_sync, + + -- UTH + g_uth_len_max => g_uth_len_max, + g_uth_typ_ofs => g_uth_typ_ofs + ) + PORT MAP ( + chip_id => chip_id, + + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + dp_sync => dp_pps, + tr_clk => tr_mesh_clk, + cal_clk => cal_clk, + + -- User interface (4 nodes)(4 input streams) + tx_usr_siso_2arr => tx_usr_siso_2arr, + tx_usr_sosi_2arr => tx_usr_sosi_2arr, -- <== Data to the Mesh + rx_usr_siso_2arr => rx_usr_siso_2arr, + rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- ==> Data from the Mesh + + -- Serial (tr_nonbonded) + tx_serial_2arr => tx_serial_2arr, + rx_serial_2arr => rx_serial_2arr, + + -- MM Control + -- . tr_nonbonded + reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi, + reg_tr_nonbonded_miso => reg_tr_nonbonded_miso, + reg_diagnostics_mosi => reg_diagnostics_mosi, + reg_diagnostics_miso => reg_diagnostics_miso, + + -- . monitor data buffer + ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi, + ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso + ); + + ---------------------------------------------------------------------------- + -- Sink: data buffer real + ---------------------------------------------------------------------------- + u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer + GENERIC MAP ( + g_nof_streams => c_db_nof_streams, + g_data_type => c_db_data_type_re, + g_data_w => c_db_data_w, + g_buf_nof_data => c_db_nof_data, + g_buf_use_sync => TRUE + ) + PORT MAP ( + -- System + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + -- MM interface + ram_data_buf_mosi => ram_diag_data_buf_re_mosi, + ram_data_buf_miso => ram_diag_data_buf_re_miso, + reg_data_buf_mosi => reg_diag_data_buf_re_mosi, + reg_data_buf_miso => reg_diag_data_buf_re_miso, + -- ST interface + in_sync => db_snk_in_arr(0).sync, + in_sosi_arr => db_snk_in_arr + ); + + ---------------------------------------------------------------------------- + -- Sink: data buffer imag + ---------------------------------------------------------------------------- + u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer + GENERIC MAP ( + g_nof_streams => c_db_nof_streams, + g_data_type => c_db_data_type_im, + g_data_w => c_db_data_w, + g_buf_nof_data => c_db_nof_data, + g_buf_use_sync => TRUE + ) + PORT MAP ( + -- System + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_rst => dp_rst, + dp_clk => dp_clk, + -- MM interface + ram_data_buf_mosi => ram_diag_data_buf_im_mosi, + ram_data_buf_miso => ram_diag_data_buf_im_miso, + reg_data_buf_mosi => reg_diag_data_buf_im_mosi, + reg_data_buf_miso => reg_diag_data_buf_im_miso, + -- ST interface + in_sync => db_snk_in_arr(0).sync, + in_sosi_arr => db_snk_in_arr + ); + + +END str;