Added DDR3 single rank master and slave

libraries/technology/ddr/hdllib.cfg

@@ -2,6 +2,8 @@ hdl_lib_name = tech_ddr
 hdl_library_clause_name = tech_ddr_lib
 hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
                      ip_stratixiv_ddr3_uphy_4g_800_slave
+                     ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+                     ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
                      ip_stratixiv_ddr3_mem_model
                      ip_arria10_ddr4_4g_1600
                      ip_arria10_ddr4_8g_2400
@@ -16,7 +18,6 @@ synth_files =
     tech_ddr_component_pkg.vhd
     tech_ddr_stratixiv.vhd
     tech_ddr_arria10.vhd
-    
     tech_ddr.vhd
 
 test_bench_files =