From 1188f0b965754d6c9b4b1ac3e09fcee694388250 Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Wed, 22 Apr 2015 13:10:19 +0000
Subject: [PATCH] Added DDR3 single rank master and slave
---
libraries/technology/ddr/hdllib.cfg | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index 2bde7d32da..45a01e6d39 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -1,12 +1,14 @@
hdl_lib_name = tech_ddr
hdl_library_clause_name = tech_ddr_lib
hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
- ip_stratixiv_ddr3_uphy_4g_800_slave
- ip_stratixiv_ddr3_mem_model
- ip_arria10_ddr4_4g_1600
- ip_arria10_ddr4_8g_2400
- ip_arria10_ddr4_mem_model_141
- common
+ ip_stratixiv_ddr3_uphy_4g_800_slave
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
+ ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
+ ip_stratixiv_ddr3_mem_model
+ ip_arria10_ddr4_4g_1600
+ ip_arria10_ddr4_8g_2400
+ ip_arria10_ddr4_mem_model_141
+ common
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -16,7 +18,6 @@ synth_files =
tech_ddr_component_pkg.vhd
tech_ddr_stratixiv.vhd
tech_ddr_arria10.vhd
-
tech_ddr.vhd
test_bench_files =
--
GitLab