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Commit 110c4345 authored by Eric Kooistra's avatar Eric Kooistra
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Move io/tr_xaui/src/vhdl/tr_xaui_align_dly.vhd to technology/xaui/tech_xaui_align_dly.vhd.

parent 1b530793
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......@@ -11,7 +11,6 @@ modelsim_search_libraries =
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
synth_files =
src/vhdl/tr_xaui_align_dly.vhd
src/vhdl/tr_xaui_deframer.vhd
src/vhdl/tr_xaui_framer.vhd
src/vhdl/tr_xaui_mdio.vhd
......
......@@ -202,18 +202,6 @@ BEGIN
src_out => rx_sosi_arr(i)
);
u_tr_xaui_align_dly: ENTITY work.tr_xaui_align_dly
GENERIC MAP(
g_sim => g_sim
)
PORT MAP(
tx_rst => i_tx_rst_arr(i),
tx_clk => tx_clk_arr(i),
a_rx_channelaligned => txc_rx_channelaligned_arr(i),
txc_rx_channelaligned_dly => txc_rx_channelaligned_dly_arr(i)
);
END GENERATE; -- g_nof_xaui
END GENERATE;
......
......@@ -9,6 +9,7 @@ build_dir_synth = $HDL_BUILD_DIR
synth_files =
sim_xaui.vhd
tech_xaui_component_pkg.vhd
tech_xaui_align_dly.vhd
tech_xaui_stratixiv.vhd
tech_xaui.vhd
......
......@@ -28,6 +28,7 @@ USE common_lib.common_interface_layers_pkg.ALL;
ENTITY sim_xaui IS
GENERIC(
g_sim : BOOLEAN := FALSE;
g_nof_xaui : NATURAL := 1
);
PORT (
......
......@@ -80,7 +80,7 @@ BEGIN
gen_ip_stratixiv : IF c_use_technology=TRUE AND g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_xaui_stratixiv
GENERIC MAP (g_nof_xaui)
GENERIC MAP (g_sim, g_nof_xaui)
PORT MAP (tr_clk, tr_rst, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
tx_clk_arr, rx_clk_arr_out, rx_clk_arr_in, txc_tx_ready_arr, rxc_rx_ready_arr, txc_rx_channelaligned_arr,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
......@@ -90,7 +90,7 @@ BEGIN
gem_sim_xaui : IF c_use_sim_model=TRUE GENERATE
u0 : ENTITY work.sim_xaui
GENERIC MAP (g_nof_xaui)
GENERIC MAP (g_sim, g_nof_xaui)
PORT MAP (tr_clk, tr_rst, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
tx_clk_arr, rx_clk_arr_out, rx_clk_arr_in, txc_tx_ready_arr, rxc_rx_ready_arr, txc_rx_channelaligned_arr,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
......
......@@ -22,7 +22,7 @@
-- Purpose: Define that other side must be aligned within some delay after this side got aligned.
-- Description:
-- We assume the RX connected to our TX will be channel aligned within c_align_dly_cnt cycles
-- We assume the RX connected to our TX will be channel aligned within g_align_dly_cnt cycles
-- after 'our own' RX has asserted channelaligned. This is important because txc_tx_channelaligned_dly
-- connects directly to tx_siso.ready.
-- Assert txc_rx_channelaligned: basically indicates whether or not the RX of the receiving
......@@ -33,9 +33,9 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
ENTITY tr_xaui_align_dly IS
ENTITY tech_xaui_align_dly IS
GENERIC(
g_sim : BOOLEAN
g_align_dly_cnt : NATURAL := 156250000); -- about 1 second on hw
);
PORT (
tx_clk : IN STD_LOGIC;
......@@ -44,14 +44,13 @@ ENTITY tr_xaui_align_dly IS
a_rx_channelaligned : IN STD_LOGIC; -- rx aligned to tx from other side (asynchronous signal)
txc_rx_channelaligned_dly : OUT STD_LOGIC
);
END tr_xaui_align_dly;
END tech_xaui_align_dly;
ARCHITECTURE rtl OF tr_xaui_align_dly IS
ARCHITECTURE rtl OF tech_xaui_align_dly IS
-- FSM to delay txc_rx_channelaligned (txc_rx_channelaligned_dly is connected to tx_siso.ready)
CONSTANT c_align_dly_cnt : NATURAL := sel_a_b(g_sim, 50, 150000000); -- about 1 second on hw
CONSTANT c_align_dly_cnt_w : NATURAL := ceil_log2(c_align_dly_cnt);
CONSTANT c_align_dly_cnt_w : NATURAL := ceil_log2(g_align_dly_cnt);
TYPE t_state_enum IS (s_init, s_aligned, s_aligned_dly);
......@@ -108,7 +107,7 @@ BEGIN
WHEN s_aligned => -- We assume the connecting RX is aligned after this delay...
nxt_txc_align_dly_cycle_cnt <= INCR_UVEC(txc_align_dly_cycle_cnt, 1);
IF txc_align_dly_cycle_cnt = TO_UVEC(c_align_dly_cnt, c_align_dly_cnt_w) THEN
IF txc_align_dly_cycle_cnt = TO_UVEC(g_align_dly_cnt, c_align_dly_cnt_w) THEN
nxt_txc_rx_channelaligned_dly <= '1';
nxt_state <= s_aligned_dly;
END IF;
......
......@@ -33,6 +33,7 @@ USE work.tech_xaui_component_pkg.ALL;
ENTITY tech_xaui_stratixiv IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_nof_xaui : NATURAL := 1 -- Up to 3 (hard XAUI only) supported
);
PORT (
......@@ -125,14 +126,16 @@ BEGIN
dout => rxc_rx_ready_arr(i)
);
u_async_txc_rx_channelaligned : ENTITY common_lib.common_async
u_txc_rx_channelaligned_arr: ENTITY work.tech_xaui_align_dly
GENERIC MAP(
g_rst_level => '0'
g_align_dly_cnt => sel_a_b(g_sim, 50, 156250000); -- about 1 second on hw
)
PORT MAP(
clk => tx_clk_arr(i),
din => a_rx_channelaligned_arr(i),
dout => txc_rx_channelaligned_arr(i)
tx_rst => i_tx_rst_arr(i),
tx_clk => tx_clk_arr(i),
a_rx_channelaligned => a_rx_channelaligned_arr(i),
txc_rx_channelaligned_dly => txc_rx_channelaligned_arr(i)
);
-- IP
......
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