diff --git a/libraries/io/tr_xaui/hdllib.cfg b/libraries/io/tr_xaui/hdllib.cfg
index d4c6d1f6b1dce6a0c16fc68d44c76da80997b956..fb56429301373fbd2c56a7c43d224b1d83d3e466 100644
--- a/libraries/io/tr_xaui/hdllib.cfg
+++ b/libraries/io/tr_xaui/hdllib.cfg
@@ -11,7 +11,6 @@ modelsim_search_libraries =
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
synth_files =
- src/vhdl/tr_xaui_align_dly.vhd
src/vhdl/tr_xaui_deframer.vhd
src/vhdl/tr_xaui_framer.vhd
src/vhdl/tr_xaui_mdio.vhd
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index ac211ceb77d6fe66c6f641e563556adb4d08f55f..626e3c926246515eef40d080bf470dadfd2d8b10 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -202,18 +202,6 @@ BEGIN
src_out => rx_sosi_arr(i)
);
-
- u_tr_xaui_align_dly: ENTITY work.tr_xaui_align_dly
- GENERIC MAP(
- g_sim => g_sim
- )
- PORT MAP(
- tx_rst => i_tx_rst_arr(i),
- tx_clk => tx_clk_arr(i),
-
- a_rx_channelaligned => txc_rx_channelaligned_arr(i),
- txc_rx_channelaligned_dly => txc_rx_channelaligned_dly_arr(i)
- );
END GENERATE; -- g_nof_xaui
END GENERATE;
diff --git a/libraries/technology/xaui/hdllib.cfg b/libraries/technology/xaui/hdllib.cfg
index 056052dce92899dfc682bfbc40e98af8be6f449f..0929c61d2b0a0f2d68d7baa3df14d772f40b8284 100644
--- a/libraries/technology/xaui/hdllib.cfg
+++ b/libraries/technology/xaui/hdllib.cfg
@@ -9,6 +9,7 @@ build_dir_synth = $HDL_BUILD_DIR
synth_files =
sim_xaui.vhd
tech_xaui_component_pkg.vhd
+ tech_xaui_align_dly.vhd
tech_xaui_stratixiv.vhd
tech_xaui.vhd
diff --git a/libraries/technology/xaui/sim_xaui.vhd b/libraries/technology/xaui/sim_xaui.vhd
index 5e0db49adb827f9e3ef242e0991bebd80204dcd9..21fec43c35b0dd9eb58440f12e42fd6a971b17e4 100644
--- a/libraries/technology/xaui/sim_xaui.vhd
+++ b/libraries/technology/xaui/sim_xaui.vhd
@@ -28,6 +28,7 @@ USE common_lib.common_interface_layers_pkg.ALL;
ENTITY sim_xaui IS
GENERIC(
+ g_sim : BOOLEAN := FALSE;
g_nof_xaui : NATURAL := 1
);
PORT (
diff --git a/libraries/technology/xaui/tech_xaui.vhd b/libraries/technology/xaui/tech_xaui.vhd
index b9101b9c87039107d798b4f5078d0c4cf86039dc..7c06cd00d7f27f3482a7ba2d603c9256ebee2073 100644
--- a/libraries/technology/xaui/tech_xaui.vhd
+++ b/libraries/technology/xaui/tech_xaui.vhd
@@ -80,7 +80,7 @@ BEGIN
gen_ip_stratixiv : IF c_use_technology=TRUE AND g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_xaui_stratixiv
- GENERIC MAP (g_nof_xaui)
+ GENERIC MAP (g_sim, g_nof_xaui)
PORT MAP (tr_clk, tr_rst, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
tx_clk_arr, rx_clk_arr_out, rx_clk_arr_in, txc_tx_ready_arr, rxc_rx_ready_arr, txc_rx_channelaligned_arr,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
@@ -90,7 +90,7 @@ BEGIN
gem_sim_xaui : IF c_use_sim_model=TRUE GENERATE
u0 : ENTITY work.sim_xaui
- GENERIC MAP (g_nof_xaui)
+ GENERIC MAP (g_sim, g_nof_xaui)
PORT MAP (tr_clk, tr_rst, cal_rec_clk, mm_clk, mm_rst, xaui_mosi, xaui_miso,
tx_clk_arr, rx_clk_arr_out, rx_clk_arr_in, txc_tx_ready_arr, rxc_rx_ready_arr, txc_rx_channelaligned_arr,
xgmii_tx_dc_arr, xgmii_rx_dc_arr,
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_align_dly.vhd b/libraries/technology/xaui/tech_xaui_align_dly.vhd
similarity index 91%
rename from libraries/io/tr_xaui/src/vhdl/tr_xaui_align_dly.vhd
rename to libraries/technology/xaui/tech_xaui_align_dly.vhd
index 3025e1f567071000945698d911478dc97b1c99cf..6cad211e8bd3259c50f164f07d04f3c053b6e46a 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_align_dly.vhd
+++ b/libraries/technology/xaui/tech_xaui_align_dly.vhd
@@ -22,7 +22,7 @@
-- Purpose: Define that other side must be aligned within some delay after this side got aligned.
-- Description:
--- We assume the RX connected to our TX will be channel aligned within c_align_dly_cnt cycles
+-- We assume the RX connected to our TX will be channel aligned within g_align_dly_cnt cycles
-- after 'our own' RX has asserted channelaligned. This is important because txc_tx_channelaligned_dly
-- connects directly to tx_siso.ready.
-- Assert txc_rx_channelaligned: basically indicates whether or not the RX of the receiving
@@ -33,9 +33,9 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-ENTITY tr_xaui_align_dly IS
+ENTITY tech_xaui_align_dly IS
GENERIC(
- g_sim : BOOLEAN
+ g_align_dly_cnt : NATURAL := 156250000); -- about 1 second on hw
);
PORT (
tx_clk : IN STD_LOGIC;
@@ -44,14 +44,13 @@ ENTITY tr_xaui_align_dly IS
a_rx_channelaligned : IN STD_LOGIC; -- rx aligned to tx from other side (asynchronous signal)
txc_rx_channelaligned_dly : OUT STD_LOGIC
);
-END tr_xaui_align_dly;
+END tech_xaui_align_dly;
-ARCHITECTURE rtl OF tr_xaui_align_dly IS
+ARCHITECTURE rtl OF tech_xaui_align_dly IS
-- FSM to delay txc_rx_channelaligned (txc_rx_channelaligned_dly is connected to tx_siso.ready)
- CONSTANT c_align_dly_cnt : NATURAL := sel_a_b(g_sim, 50, 150000000); -- about 1 second on hw
- CONSTANT c_align_dly_cnt_w : NATURAL := ceil_log2(c_align_dly_cnt);
+ CONSTANT c_align_dly_cnt_w : NATURAL := ceil_log2(g_align_dly_cnt);
TYPE t_state_enum IS (s_init, s_aligned, s_aligned_dly);
@@ -108,7 +107,7 @@ BEGIN
WHEN s_aligned => -- We assume the connecting RX is aligned after this delay...
nxt_txc_align_dly_cycle_cnt <= INCR_UVEC(txc_align_dly_cycle_cnt, 1);
- IF txc_align_dly_cycle_cnt = TO_UVEC(c_align_dly_cnt, c_align_dly_cnt_w) THEN
+ IF txc_align_dly_cycle_cnt = TO_UVEC(g_align_dly_cnt, c_align_dly_cnt_w) THEN
nxt_txc_rx_channelaligned_dly <= '1';
nxt_state <= s_aligned_dly;
END IF;
diff --git a/libraries/technology/xaui/tech_xaui_stratixiv.vhd b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
index e520519669f413a8a2a64c2ec51b36fee7b2695f..33f4f2212c67b2297d7ebc14350ad8d5892206a6 100644
--- a/libraries/technology/xaui/tech_xaui_stratixiv.vhd
+++ b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
@@ -33,6 +33,7 @@ USE work.tech_xaui_component_pkg.ALL;
ENTITY tech_xaui_stratixiv IS
GENERIC (
+ g_sim : BOOLEAN := FALSE;
g_nof_xaui : NATURAL := 1 -- Up to 3 (hard XAUI only) supported
);
PORT (
@@ -125,16 +126,18 @@ BEGIN
dout => rxc_rx_ready_arr(i)
);
- u_async_txc_rx_channelaligned : ENTITY common_lib.common_async
+ u_txc_rx_channelaligned_arr: ENTITY work.tech_xaui_align_dly
GENERIC MAP(
- g_rst_level => '0'
+ g_align_dly_cnt => sel_a_b(g_sim, 50, 156250000); -- about 1 second on hw
)
PORT MAP(
- clk => tx_clk_arr(i),
- din => a_rx_channelaligned_arr(i),
- dout => txc_rx_channelaligned_arr(i)
- );
+ tx_rst => i_tx_rst_arr(i),
+ tx_clk => tx_clk_arr(i),
+ a_rx_channelaligned => a_rx_channelaligned_arr(i),
+ txc_rx_channelaligned_dly => txc_rx_channelaligned_arr(i)
+ );
+
-- IP
gen_hard_xaui_0: IF i=0 GENERATE
u_ip_phy_xaui : ip_stratixiv_phy_xaui_0