-Added bsn_monitor mm_file_io.

-merged transpose generics in g_reorder_seq 

applications/unb1_reorder/src/vhdl/mmm_unb1_reorder.vhd

@@ -19,7 +19,7 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib, io_ddr_lib, technology_lib, tech_ddr_lib, tech_tse_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, reorder_lib, eth_lib, io_ddr_lib, technology_lib, tech_ddr_lib, tech_tse_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -32,6 +32,7 @@ USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE reorder_lib.reorder_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
 USE tech_tse_lib.tech_tse_pkg.ALL;
@@ -40,16 +41,11 @@ USE eth_lib.eth_pkg.ALL;
 
 ENTITY mmm_unb1_reorder IS
   GENERIC (
-    g_sim           : BOOLEAN  := TRUE; --FALSE: use SOPC; TRUE: use mm_file I/O
-    g_sim_unb_nr    : NATURAL  := 0;
-    g_wr_chunksize  : POSITIVE := 256;
-    g_wr_nof_chunks : POSITIVE := 1;  
-    g_rd_chunksize  : POSITIVE := 32;
-    g_rd_nof_chunks : POSITIVE := 8;  
-    g_sim_node_nr   : NATURAL  := 0;
-    g_nof_streams   : NATURAL  := 4;
-    g_nof_MB        : NATURAL  := 2;
-    g_frame_size_in : NATURAL  := 256         
+    g_sim         : BOOLEAN  := TRUE; --FALSE: use SOPC; TRUE: use mm_file I/O
+    g_sim_unb_nr  : NATURAL  := 0;
+    g_sim_node_nr : NATURAL  := 0;
+    g_nof_streams : NATURAL  := 4;
+    g_reorder_seq : t_reorder_seq := c_reorder_seq         
    );
   PORT (
     -- GENERAL
@@ -122,19 +118,14 @@ END mmm_unb1_reorder;
 
 ARCHITECTURE str OF mmm_unb1_reorder IS
 
-  CONSTANT c_stimuli_length            : POSITIVE := g_wr_nof_chunks * g_wr_chunksize * g_rd_chunksize;
-  CONSTANT c_nof_MB                    : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control intrastructure for two MB's
-  CONSTANT c_reg_diag_bg_adr_w         : NATURAL  := 3;
-  CONSTANT c_ram_diag_bg_adr_w         : POSITIVE := ceil_log2(g_nof_streams * c_stimuli_length);
+  CONSTANT c_stimuli_length             : POSITIVE := g_reorder_seq.wr_chunksize * g_reorder_seq.rd_chunksize; -- 256 x 32 = 8192
+  CONSTANT c_reg_diag_bg_adr_w          : NATURAL  := 3;
+  CONSTANT c_ram_diag_bg_adr_w          : POSITIVE := ceil_log2(g_nof_streams * c_stimuli_length);
   CONSTANT c_reg_diag_data_buf_im_adr_w : NATURAL  := 5;
   CONSTANT c_ram_diag_data_buf_im_adr_w : NATURAL  := ceil_log2(g_nof_streams * c_stimuli_length);
   CONSTANT c_reg_diag_data_buf_re_adr_w : NATURAL  := 5;
   CONSTANT c_ram_diag_data_buf_re_adr_w : NATURAL  := ceil_log2(g_nof_streams * c_stimuli_length);
-  CONSTANT c_ram_ss_ss_transp_adr_w     : NATURAL  := ceil_log2(g_frame_size_in * g_rd_chunksize);
-
-  -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
-  CONSTANT c_mm_reg_ddr3_addr_w        : NATURAL := ceil_log2(7);
-  CONSTANT c_mm_reg_diagnostics_addr_w : NATURAL := ceil_log2(40);
+  CONSTANT c_ram_ss_ss_transp_adr_w     : NATURAL  := ceil_log2(g_reorder_seq.wr_chunksize * g_reorder_seq.rd_chunksize);
 
   -- Simulation
   CONSTANT c_mm_clk_period             : TIME := 500 ps;
@@ -234,6 +225,10 @@ BEGIN
 
     u_mm_file_ram_ss_ss_transp     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
                                              PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+
+    u_mm_file_reg_bsn_monitor      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+                                             PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
+
     ----------------------------------------------------------------------------
     -- 1GbE setup sequence normally performed by unb_os@NIOS
     ----------------------------------------------------------------------------
@@ -422,7 +417,7 @@ BEGIN
       coe_writedata_export_from_the_ram_ss_ss_wide     => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
       
       -- the_reg_bsn_monitor
-      coe_address_export_from_the_reg_bsn_monitor      => reg_bsn_monitor_mosi.address(1+c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
+      coe_address_export_from_the_reg_bsn_monitor      => reg_bsn_monitor_mosi.address(3+c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
       coe_clk_export_from_the_reg_bsn_monitor          => OPEN,
       coe_read_export_from_the_reg_bsn_monitor         => reg_bsn_monitor_mosi.rd,
       coe_readdata_export_to_the_reg_bsn_monitor       => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),