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Commit 102b1123 authored by Pieter Donker's avatar Pieter Donker
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Merge branch 'L2SDP-455' into 'master' 

Resolve L2SDP-455

Closes L2SDP-455

See merge request desp/hdl!134
parents ce6b96ee 2640914a
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1 merge request!134Resolve L2SDP-455
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applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+ 40
− 40
View file @ 102b1123
......@@ -99,7 +99,7 @@
{
datum baseAddress
{
value = "737752";
value = "737760";
type = "String";
}
}
......@@ -144,7 +144,7 @@
{
datum baseAddress
{
value = "737672";
value = "737688";
type = "String";
}
}
......@@ -157,7 +157,7 @@
}
datum sopceditor_expanded
{
value = "0";
value = "1";
type = "boolean";
}
}
......@@ -165,7 +165,7 @@
{
datum baseAddress
{
value = "737744";
value = "737648";
type = "String";
}
}
......@@ -426,7 +426,7 @@
{
datum baseAddress
{
value = "737696";
value = "737712";
type = "String";
}
}
......@@ -442,7 +442,7 @@
{
datum baseAddress
{
value = "737648";
value = "737664";
type = "String";
}
}
......@@ -506,7 +506,7 @@
{
datum baseAddress
{
value = "737688";
value = "737704";
type = "String";
}
}
......@@ -538,7 +538,7 @@
{
datum baseAddress
{
value = "737656";
value = "737672";
type = "String";
}
}
......@@ -575,7 +575,7 @@
{
datum baseAddress
{
value = "737736";
value = "737752";
type = "String";
}
}
......@@ -596,7 +596,7 @@
{
datum baseAddress
{
value = "737728";
value = "737744";
type = "String";
}
}
......@@ -691,7 +691,7 @@
{
datum baseAddress
{
value = "737720";
value = "737736";
type = "String";
}
}
......@@ -712,7 +712,7 @@
{
datum baseAddress
{
value = "737712";
value = "737728";
type = "String";
}
}
......@@ -728,7 +728,7 @@
{
datum baseAddress
{
value = "737680";
value = "737696";
type = "String";
}
}
......@@ -797,7 +797,7 @@
{
datum baseAddress
{
value = "737704";
value = "737720";
type = "String";
}
}
......@@ -829,7 +829,7 @@
{
datum baseAddress
{
value = "737664";
value = "737680";
type = "String";
}
}
......@@ -1291,11 +1291,6 @@
internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
<interface
name="reg_stat_hdr_dat_xst_readdata"
internal="reg_stat_hdr_dat_xst.readdata"
type="conduit"
dir="end" />
<interface
name="ram_bf_weights_address"
internal="ram_bf_weights.address"
......@@ -2671,6 +2666,11 @@
internal="reg_stat_hdr_dat_xst.read"
type="conduit"
dir="end" />
<interface
name="reg_stat_hdr_dat_xst_readdata"
internal="reg_stat_hdr_dat_xst.readdata"
type="conduit"
dir="end" />
<interface
name="reg_stat_hdr_dat_xst_reset"
internal="reg_stat_hdr_dat_xst.reset"
......@@ -5805,7 +5805,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /&gt;&lt;slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0xB4170' end='0xB4180' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler_xsub.mem' start='0xB4180' end='0xB4188' datawidth='32' /&gt;&lt;slave name='reg_dp_sync_insert_v2.mem' start='0xB4188' end='0xB4190' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0xB4190' end='0xB4198' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0xB4198' end='0xB41A0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41E0' end='0xB41E8' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
......@@ -8448,7 +8448,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
......@@ -8512,7 +8512,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
<width>1</width>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
......@@ -8581,7 +8581,7 @@
</entry>
<entry>
<key>addressSpan</key>
<value>8</value>
<value>16</value>
</entry>
<entry>
<key>addressUnits</key>
......@@ -8987,11 +8987,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
<value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>3</value>
<value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
......@@ -39356,7 +39356,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="baseAddress" value="0x000b41d8" />
<parameter name="baseAddress" value="0x000b41e0" />
</connection>
<connection
kind="avalon"
......@@ -39391,7 +39391,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="baseAddress" value="0x000b41d0" />
<parameter name="baseAddress" value="0x000b4170" />
</connection>
<connection
kind="avalon"
......@@ -39419,28 +39419,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="baseAddress" value="0x000b41c8" />
<parameter name="baseAddress" value="0x000b41d8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="baseAddress" value="0x000b41c0" />
<parameter name="baseAddress" value="0x000b41d0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="baseAddress" value="0x000b41b8" />
<parameter name="baseAddress" value="0x000b41c8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="baseAddress" value="0x000b41b0" />
<parameter name="baseAddress" value="0x000b41c0" />
</connection>
<connection
kind="avalon"
......@@ -39475,7 +39475,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="baseAddress" value="0x000b41a8" />
<parameter name="baseAddress" value="0x000b41b8" />
</connection>
<connection
kind="avalon"
......@@ -39517,7 +39517,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="baseAddress" value="0x000b41a0" />
<parameter name="baseAddress" value="0x000b41b0" />
</connection>
<connection
kind="avalon"
......@@ -39552,7 +39552,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="baseAddress" value="0x000b4198" />
<parameter name="baseAddress" value="0x000b41a8" />
</connection>
<connection
kind="avalon"
......@@ -39615,7 +39615,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="baseAddress" value="0x000b4190" />
<parameter name="baseAddress" value="0x000b41a0" />
</connection>
<connection
kind="avalon"
......@@ -39643,14 +39643,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="baseAddress" value="0x000b4188" />
<parameter name="baseAddress" value="0x000b4198" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="baseAddress" value="0x000b4180" />
<parameter name="baseAddress" value="0x000b4190" />
</connection>
<connection
kind="avalon"
......@@ -39678,7 +39678,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_sync_insert_v2.mem">
<parameter name="baseAddress" value="0x000b4178" />
<parameter name="baseAddress" value="0x000b4188" />
</connection>
<connection
kind="avalon"
......@@ -39692,7 +39692,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler_xsub.mem">
<parameter name="baseAddress" value="0x000b4170" />
<parameter name="baseAddress" value="0x000b4180" />
</connection>
<connection
kind="avalon"
applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+ 1
− 3
View file @ 102b1123
......@@ -479,9 +479,7 @@ BEGIN
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
-- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 DOWNTO 0),
-- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+ 1
− 1
View file @ 102b1123
......@@ -62,7 +62,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
pio_jesd_ctrl_reset_export : out std_logic; -- export
pio_jesd_ctrl_write_export : out std_logic; -- export
pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
pio_pps_clk_export : out std_logic; -- export
pio_pps_read_export : out std_logic; -- export
pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
......
boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+ 1
− 1
View file @ 102b1123
......@@ -61,7 +61,7 @@ PACKAGE unb2b_board_peripherals_pkg IS
reg_common_adr_w : NATURAL; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
-- pi_ppsh
reg_ppsh_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
reg_ppsh_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in ppsh_reg
-- pi_unb_sens
reg_unb_sens_adr_w : NATURAL; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
......
boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+ 1
− 1
View file @ 102b1123
......@@ -61,7 +61,7 @@ PACKAGE unb2c_board_peripherals_pkg IS
reg_common_adr_w : NATURAL; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
-- pi_ppsh
reg_ppsh_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
reg_ppsh_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in ppsh_reg
-- pi_unb_sens
reg_unb_sens_adr_w : NATURAL; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
......
libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
+ 53
− 45
View file @ 102b1123
......@@ -32,13 +32,18 @@ END tb_mms_ppsh;
ARCHITECTURE tb OF tb_mms_ppsh IS
CONSTANT c_clk_freq : NATURAL := 1000; -- clock frequency in Hz
CONSTANT c_clk_period : TIME := 1000000 us / c_clk_freq;
CONSTANT c_pps_period : NATURAL := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
CONSTANT c_st_clk_freq : NATURAL := 1000; -- clock frequency in Hz
CONSTANT c_st_clk_period : TIME := 1000000 us / c_st_clk_freq;
CONSTANT c_mm_clk_period : TIME := c_st_clk_period * 3; -- somewhat slower mm_clk
CONSTANT c_pps_period : NATURAL := c_st_clk_freq; -- 1 s takes c_clk_freq clk cycles
CONSTANT c_cnt_w : NATURAL := ceil_log2(c_st_clk_freq);
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL mm_rst : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '1';
SIGNAL st_rst : STD_LOGIC := '1';
SIGNAL st_clk : STD_LOGIC := '1';
-- DUT
SIGNAL pps_ext : STD_LOGIC;
......@@ -48,7 +53,7 @@ ARCHITECTURE tb OF tb_mms_ppsh IS
SIGNAL reg_miso : t_mem_miso;
-- Verify
SIGNAL bsn : NATURAL;
SIGNAL bsn : NATURAL; -- block sequence number counts seconds
SIGNAL pps_toggle : STD_LOGIC;
SIGNAL pps_stable : STD_LOGIC;
SIGNAL capture_cnt : NATURAL;
......@@ -65,8 +70,10 @@ BEGIN
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
rst <= '1', '0' AFTER 7*c_clk_period;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
st_rst <= '1', '0' AFTER 7*c_st_clk_period;
st_clk <= NOT st_clk OR tb_end AFTER c_st_clk_period/2;
mm_rst <= '1', '0' AFTER 7*c_mm_clk_period;
mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
p_pps_ext : PROCESS
VARIABLE v_pps_period : NATURAL := c_pps_period;
......@@ -81,10 +88,10 @@ BEGIN
ELSIF bsn = 69 THEN
v_pps_period := c_pps_period+1;
END IF;
proc_common_wait_some_cycles(clk, v_pps_period-1);
proc_common_wait_some_cycles(st_clk, v_pps_period-1);
pps_ext <= '1';
bsn <= bsn + 1;
proc_common_wait_some_cycles(clk, 1);
proc_common_wait_some_cycles(st_clk, 1);
pps_ext <= '0';
END LOOP;
......@@ -94,88 +101,89 @@ BEGIN
p_mm_stimuli : PROCESS
VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
BEGIN
proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
proc_common_wait_until_low(st_clk, st_rst); -- Wait until reset has finished
proc_common_wait_until_low(mm_clk, mm_rst); -- Wait until reset has finished
proc_common_wait_some_cycles(mm_clk, 10); -- Wait an additional amount of cycles
v_word := '0' & TO_UVEC(c_pps_period, 31); -- capture_edge = '0' = at rising edge
-- expected_cnt = c_pps_period = 1000
proc_mem_mm_bus_wr(1, v_word, clk, reg_mosi);
proc_mem_mm_bus_wr(1, v_word, mm_clk, reg_mosi);
-- Simulate reading PPS status every 10 PPS periods
proc_common_wait_some_cycles(clk, 10);
proc_common_wait_some_cycles(st_clk, 10);
FOR I IN 0 TO 9 LOOP
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
proc_mem_mm_bus_rd(0, clk, reg_mosi);
proc_common_wait_some_cycles(clk, 1);
proc_mem_mm_bus_rd(0, mm_clk, reg_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
pps_toggle <= reg_miso.rddata(31);
pps_stable <= reg_miso.rddata(30);
capture_cnt <= TO_UINT(reg_miso.rddata(ceil_log2(c_clk_freq)-1 DOWNTO 0));
capture_cnt <= TO_UINT(reg_miso.rddata(c_cnt_w-1 DOWNTO 0));
END LOOP;
-- Simulate reading PPS offset counter every 0.1 PPS periods
proc_common_wait_some_cycles(clk, 10);
FOR I IN 0 TO 4 LOOP
proc_common_wait_some_cycles(clk, c_pps_period/10);
-- Simulate reading PPS offset counter every 0.25 PPS periods
proc_common_wait_some_cycles(st_clk, 10);
FOR I IN 0 TO 40 LOOP
proc_common_wait_some_cycles(st_clk, c_pps_period/4);
last_offset_cnt <= offset_cnt;
proc_mem_mm_bus_rd(2, clk, reg_mosi);
proc_common_wait_some_cycles(clk, 1);
offset_cnt <= TO_UINT(reg_miso.rddata(ceil_log2(c_clk_freq)-1 DOWNTO 0));
proc_mem_mm_bus_rd(2, mm_clk, reg_mosi);
proc_common_wait_some_cycles(mm_clk, 1);
offset_cnt <= TO_UINT(reg_miso.rddata(c_cnt_w-1 DOWNTO 0));
END LOOP;
proc_common_wait_some_cycles(clk, 100);
proc_common_wait_some_cycles(st_clk, 100);
tb_end <= '1';
WAIT;
END PROCESS;
p_verify : PROCESS
BEGIN
proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
proc_common_wait_until_low(st_clk, st_rst); -- Wait until reset has finished
proc_common_wait_some_cycles(st_clk, 10); -- Wait an additional amount of cycles
proc_common_wait_some_cycles(clk, c_pps_period/2); -- Verification offset
proc_common_wait_some_cycles(st_clk, c_pps_period/2); -- Verification offset
-- 1
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "1) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "1) Wrong capture_cnt" SEVERITY ERROR;
-- 2
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "2) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "2) Wrong capture_cnt" SEVERITY ERROR;
-- 3
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "3) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=999 REPORT "3) Wrong capture_cnt" SEVERITY ERROR;
-- 4
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "4) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "4) Wrong capture_cnt" SEVERITY ERROR;
-- 5
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "5) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "5) Wrong capture_cnt" SEVERITY ERROR;
-- 6
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "6) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "6) Wrong capture_cnt" SEVERITY ERROR;
-- 7
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "7) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1001 REPORT "7) Wrong capture_cnt" SEVERITY ERROR;
-- 8
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "8) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "8) Wrong capture_cnt" SEVERITY ERROR;
-- 9
proc_common_wait_some_cycles(clk, c_pps_period*10);
proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "9) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "9) Wrong capture_cnt" SEVERITY ERROR;
-- 10
proc_common_wait_some_cycles(clk, c_pps_period/10);
proc_common_wait_some_cycles(st_clk, c_pps_period/10);
ASSERT offset_cnt=last_offset_cnt REPORT "10) Wrong offset_cnt" SEVERITY ERROR;
-- 11
proc_common_wait_some_cycles(clk, c_pps_period/10);
proc_common_wait_some_cycles(st_clk, c_pps_period/10);
ASSERT offset_cnt=last_offset_cnt REPORT "11) Wrong offset_cnt" SEVERITY ERROR;
WAIT;
END PROCESS;
......@@ -187,14 +195,14 @@ BEGIN
dut : ENTITY work.mms_ppsh
GENERIC MAP (
g_st_clk_freq => c_clk_freq
g_st_clk_freq => c_st_clk_freq
)
PORT MAP (
-- Clocks and reset
mm_rst => rst,
mm_clk => clk,
st_rst => rst,
st_clk => clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => st_rst,
st_clk => st_clk,
pps_ext => pps_ext,
-- Memory-mapped clock domain
......
libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
+ 60
− 12
View file @ 102b1123
......@@ -33,6 +33,7 @@ ARCHITECTURE tb OF tb_ppsh IS
CONSTANT c_clk_period : TIME := 1000000 us / c_clk_freq;
CONSTANT c_pps_default_period : NATURAL := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
CONSTANT c_pps_skew : TIME := 7*c_clk_period/10;
CONSTANT c_cnt_w : NATURAL := ceil_log2(c_clk_freq);
-- The state name tells what kind of test is being done
TYPE t_state_enum IS (
......@@ -54,11 +55,15 @@ ARCHITECTURE tb OF tb_ppsh IS
SIGNAL pps_ext : STD_LOGIC;
SIGNAL pps_sys : STD_LOGIC;
SIGNAL pps_toggle : STD_LOGIC;
SIGNAL pps_stable : STD_LOGIC;
SIGNAL pps_stable_ack : STD_LOGIC := '0';
SIGNAL capture_edge : STD_LOGIC;
SIGNAL capture_cnt : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
SIGNAL offset_cnt : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
SIGNAL capture_cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
SIGNAL offset_cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
SIGNAL expected_cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
-- Verify
SIGNAL verify_s : REAL := 0.0; -- provides time line marker for p_verify in Wave Window
BEGIN
......@@ -73,13 +78,44 @@ BEGIN
-- Verify that using the falling capture edge indeed does change timing by
-- using a c_pps_skew that is > 0.5 c_clk_period and < c_clk_period
capture_edge <= '0', '1' AFTER 5000 ms, '0' AFTER 7000 ms;
p_capture_edge : PROCESS
BEGIN
capture_edge <= '0';
WAIT FOR 5000 ms;
capture_edge <= '1'; -- will be verified by p_verify
WAIT FOR 2000 ms;
capture_edge <= '0';
WAIT;
END PROCESS;
p_verify_pps_stable : PROCESS
BEGIN
pps_stable_ack <= '0';
WAIT FOR 9000 ms; -- wait until p_capture_edge is done
IF pps_stable /= '0' THEN
REPORT "PPSH : Unexpected pps_stable, should be 0." SEVERITY ERROR;
END IF;
-- ack PPS stable monitor
pps_stable_ack <= '1';
WAIT FOR 1*c_clk_period;
pps_stable_ack <= '0';
WAIT FOR 10 ms;
IF pps_stable /= '1' THEN
REPORT "PPSH : Unexpected pps_stable, should be 1." SEVERITY ERROR;
END IF;
WAIT FOR 13000 ms; -- wait until first loop in p_pps_default_period is done
IF pps_stable /= '0' THEN
REPORT "PPSH : Unexpected pps_stable, should have become 0." SEVERITY ERROR;
END IF;
WAIT;
END PROCESS;
-- Verify the capture_cnt
p_pps_default_period : PROCESS
BEGIN
tb_state <= s_idle;
pps <= '0';
expected_cnt <= TO_UVEC(c_pps_default_period, c_cnt_w);
WAIT UNTIL rst='0';
WAIT FOR 10*c_clk_period;
WAIT UNTIL rising_edge(clk); -- get synchronous to clk
......@@ -130,8 +166,6 @@ BEGIN
pps <= '0';
WAIT FOR (c_pps_default_period-I)*c_clk_period;
END LOOP;
-- Missing PPS pulses
tb_state <= s_missing_pps;
-- End
tb_state <= s_end;
......@@ -158,11 +192,14 @@ BEGIN
-- PPS
pps_ext => pps_ext,
pps_sys => pps_sys,
pps_toggle => pps_toggle,
-- MM control
capture_edge => capture_edge,
capture_cnt => capture_cnt,
offset_cnt => offset_cnt
pps_toggle => pps_toggle,
pps_stable => pps_stable,
pps_stable_ack => pps_stable_ack,
capture_edge => capture_edge,
capture_cnt => capture_cnt,
offset_cnt => offset_cnt,
expected_cnt => expected_cnt
);
-----------------------------------------------------------------------------
......@@ -187,18 +224,21 @@ BEGIN
IF UNSIGNED(capture_cnt)/=c_clk_freq+1 THEN
REPORT "PPSH : Unexpected capture count value at 6 s." SEVERITY ERROR;
END IF;
verify_s <= 6.0;
END IF;
IF (NOW > 7000 ms) AND (NOW <= 7000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 7 s." SEVERITY ERROR;
END IF;
verify_s <= 7.0;
END IF;
IF (NOW > 8000 ms) AND (NOW <= 8000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq-1 THEN
REPORT "PPSH : Unexpected capture count value at 8 s." SEVERITY ERROR;
END IF;
verify_s <= 8.0;
END IF;
-- Verify external PPS period fluctuations at specific stimuli moments
......@@ -206,57 +246,65 @@ BEGIN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 10 s." SEVERITY ERROR;
END IF;
verify_s <= 10.0;
END IF;
IF (NOW > 22000 ms) AND (NOW <= 22000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq-1 THEN
REPORT "PPSH : Unexpected capture count value at 22 s." SEVERITY ERROR;
END IF;
verify_s <= 22.0;
END IF;
IF (NOW > 25000 ms) AND (NOW <= 25000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 25 s." SEVERITY ERROR;
END IF;
verify_s <= 25.0;
END IF;
IF (NOW > 28000 ms) AND (NOW <= 28000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq+1 THEN
REPORT "PPSH : Unexpected capture count value at 28 s." SEVERITY ERROR;
END IF;
verify_s <= 28.0;
END IF;
IF (NOW > 30000 ms) AND (NOW <= 30000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 30 s." SEVERITY ERROR;
END IF;
verify_s <= 30.0;
END IF;
IF (NOW > 35000 ms) AND (NOW <= 35000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value at 35 s." SEVERITY ERROR;
END IF;
verify_s <= 35.0;
END IF;
IF (NOW > 49000 ms) AND (NOW <= 49000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value at 49 s." SEVERITY ERROR;
END IF;
verify_s <= 49.0;
END IF;
-- check if offset_cnt is counting
IF (NOW > 7500 ms) AND (NOW <= 7500 ms + c_clk_period) THEN
IF UNSIGNED(offset_cnt)/=475 THEN
REPORT "PPSH : Unexpected offset count value at 5.5 s." SEVERITY ERROR;
REPORT "PPSH : Unexpected offset count value at 7.5 s." SEVERITY ERROR;
END IF;
verify_s <= 7.5;
END IF;
IF (NOW > 7700 ms) AND (NOW <= 7700 ms + c_clk_period) THEN
IF UNSIGNED(offset_cnt)/=675 THEN
REPORT "PPSH : Unexpected offset count value at 5.5 s." SEVERITY ERROR;
REPORT "PPSH : Unexpected offset count value at 7.7 s." SEVERITY ERROR;
END IF;
verify_s <= 7.7;
END IF;
END IF;
END PROCESS;
......
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