Use DONT_CARE instead of OLD_DATA for e2sg = unb2c, like with e1sg = unb2b, to...

Use DONT_CARE instead of OLD_DATA for e2sg = unb2c, like with e1sg = unb2b, to avoid critical warning.

libraries/technology/ip_agi027_1e1v/ram/README.txt

 README.txt for $HDL_WORK/libraries/technology/ip_agi027_1e1v/ram
 VERSION 02 - 20231218
+Author: David Brouwer
 
 Contents:
 
@@ -15,9 +16,7 @@ Contents:
 10) References
 
 
-
 1) RAM components:
-
   Available:
    ip_agi027_1e1v_ram_cr_cw    = One read port with clock and one write port with clock and with separate address and same data width on both ports.
    ip_agi027_1e1v_ram_crk_cw   = One read port with clock and one write port with clock and with separate address and different data withs on both ports.
@@ -33,16 +32,13 @@ Contents:
                                  Not available, because the Agilex 7 does not support ratio widths in combination with true dual port mode.
 
 
-
 2) ROM components:
    ip_agi027_1e1v_rom_r_w      = Not available and not needed, because the ip_agi027_1e1v_ram_r_w can be used for ROM IP by not connecting the
                                  write port. The IP could be created and than the vhd file can be derived from the generated HDL files and the
                                  existing ip_stratixiv_rom_r.vhd file.
 
 
-
 3) Agilex7 IP
-
   The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_1e1v by creating it in Quartus
   using the same parameter settings by:
 
@@ -80,7 +76,6 @@ Contents:
     ip_agi027_1e1v_ram_rw_rw.ip
        is derived from the ip_arria10_e2sg_ram_crw_crw, incorporating the modification to operate with a single clock.
 
-
   The IP only needs to be generated with generate_ip_libs <buildset> if it need to be modified, because the ip_agi027_1e1v_ram_*.vhd
   directly instantiates the altera_syncram component. The buildset for the agi027_1e1v is iwave.
 
@@ -93,9 +88,7 @@ Contents:
   that is a simulation package. However it resembles how it worked for Stratix IV with altera_mf.
 
 
-
 4) Inferred IP
-
   The inferred Altera code was obtained using template insert with Quartus 14.0a10. The IPs with different port widths,
   like the ram_crk_cw, can not be inferred from RTL code.
   For the RAM the g_inferred generic is set to FALSE because the inferred instances do not yet support g_init_file.
@@ -105,9 +98,7 @@ Contents:
   to use a RAM block for implementation.
 
 
-
 5) Memory initialization file
-
   Often referred to as a .mif file. It is used to initialize the content of memory blocks within the design, specifying
   the data to be stored in each memory location. This file must be included in the Quartus Projects. During synthesis,
   the tool uses this file to iniliaze the memory blocks in the design.
@@ -125,9 +116,7 @@ Contents:
   specify the initial contents of memories in your design visually.
 
 
-
 6) Implementation options (LUTs or block RAM)
-
   The IP (and also the inferred) RAM can be set to use LUTs (MLAB), block RAM (M20K) or LCs, however this is not supported yet.
 
   . For IP RAM this would imply adding a generic to set the appropriate parameter in the altera_syncram
@@ -135,9 +124,7 @@ Contents:
     For an example see the README.txt for arria10.
 
 
-
 7) Synthesis trials
-
   All the synth .vhd files have been simulated and performed well.
   The quartus/ram.qsf could be derived from the ip_arria10/ram/ folder and changed to only the following assignments:
     set_global_assignment -name FAMILY "Agilex 7"
@@ -185,9 +172,7 @@ Contents:
         the error. [3]
 
 
-
 8) Agilex7 issues
-
   No (direct) available use of ip_agi027_1e1v_ram_crw_crw and *_crwk_crw. The other .vhd synth files based on generated HDL files of the IPs did not
   encounter any issues.
 
@@ -237,9 +222,7 @@ Contents:
       as there is also no testbench for the underlying 'common_ram_crw_crw_ratio' file that was utilized.
 
 
-
 9)    Remarks:
-
   a)  For tech_memory_ram_crw_crw the ip_agi027_1e1v_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
       It is not preferable to add an extra generic or the technology there, to generate the right used component.
       So it is better to implement a clock domain cross component such as dp_fifo_dc_arr or common_reg_cross_domain (to save logic and/or RAM)
@@ -252,9 +235,7 @@ Contents:
       This results in: one clock domain and a fixed datarate.
 
 
-
 10) References:
-
   [1] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/true-dual-port-dual-clock-emulator.html
   [2] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/embedded-memory-configurations.html
   [3] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/mixed-port-read-during-write-mode.html

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd

@@ -69,7 +69,7 @@ architecture SYN of ip_arria10_e2sg_ram_cr_cw is
           outdata_aclr_b  : string;
           outdata_reg_b  : string;
           power_up_uninitialized  : string;
-          read_during_write_mode_mixed_ports : string;
+          read_during_write_mode_mixed_ports : string;  -- use default DONT_CARE
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -115,7 +115,6 @@ begin
             outdata_aclr_b  => "NONE",
             outdata_reg_b  => c_outdata_reg_b,
             power_up_uninitialized  => "FALSE",
-            read_during_write_mode_mixed_ports => "OLD_DATA",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd

@@ -78,7 +78,7 @@ architecture SYN of ip_arria10_e2sg_ram_crw_crw is
           power_up_uninitialized  : string;
           read_during_write_mode_port_a  : string;
           read_during_write_mode_port_b  : string;
-          read_during_write_mode_mixed_ports : string;
+          read_during_write_mode_mixed_ports : string;  -- use default DONT_CARE
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -136,7 +136,6 @@ begin
             power_up_uninitialized  => "FALSE",
             read_during_write_mode_port_a  => "NEW_DATA_NO_NBE_READ",
             read_during_write_mode_port_b  => "NEW_DATA_NO_NBE_READ",
-            read_during_write_mode_mixed_ports => "OLD_DATA",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,