Merge branch 'L2SDP-197' into 'master'

Resolve L2SDP-197

Closes L2SDP-197

See merge request desp/hdl!252

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd

@@ -26,12 +26,11 @@
 --   Unb2b version for lab testing
 --   Contains complete AIT input stage with 1 ADC stream
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd

@@ -26,12 +26,11 @@
 --   Unb2b version for lab testing
 --   Use revisions to select one_node or full versions
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
@@ -43,7 +42,6 @@ ENTITY lofar2_unb2b_adc IS
     g_design_name      : STRING  := "lofar2_unb2b_adc";
     g_design_note      : STRING  := "UNUSED";
     g_jesd_freq        : STRING  := "200MHz";
-    g_technology       : NATURAL := c_tech_arria10_e1sg;
     g_buf_nof_data     : NATURAL := 1024;
     g_sim              : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr       : NATURAL := 0;
@@ -238,7 +236,6 @@ BEGIN
   u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
   GENERIC MAP (
     g_sim                => g_sim,
-    g_technology         => g_technology,
     g_design_name        => g_design_name,
     g_design_note        => g_design_note,
     g_stamp_date         => g_stamp_date,
@@ -449,7 +446,6 @@ BEGIN
 
   u_ait: ENTITY work.node_adc_input_and_timing
   GENERIC MAP(
-    g_technology                => g_technology,
     g_nof_streams               => c_nof_streams,
     g_jesd_freq                 => g_jesd_freq,
     g_sim                       => g_sim                

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd

@@ -26,12 +26,11 @@
 --   Contains all the signal processing blocks to receive and time the ADC input data
 --   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
@@ -41,7 +40,6 @@ USE lofar2_sdp_lib.sdp_pkg.ALL;
 
 ENTITY node_adc_input_and_timing IS
   GENERIC (
-    g_technology              : NATURAL := c_tech_arria10_e1sg;
     g_jesd_freq               : STRING  := "200MHz";
     g_buf_nof_data            : NATURAL := 131072; --8192; --1024;
     g_nof_streams             : NATURAL := 12;
@@ -452,7 +450,6 @@ BEGIN
 
   u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
   GENERIC MAP (
-    g_technology   => g_technology,
     g_nof_streams  => g_nof_streams,
     g_data_w       => c_data_w,
     g_buf_nof_data => g_buf_nof_data,

applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams, FSUB and BF
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams, FSUB and BF with a DP_clk of 256MHz
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd

@@ -26,14 +26,13 @@
 --   Unb2b version for lab testing
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_network_layers_pkg.ALL;
 USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
@@ -46,7 +45,6 @@ ENTITY lofar2_unb2b_beamformer IS
   GENERIC (
     g_design_name            : STRING  := "lofar2_unb2b_beamformer";
     g_design_note            : STRING  := "UNUSED";
-    g_technology             : NATURAL := c_tech_arria10_e1sg;
     g_buf_nof_data           : NATURAL := 1024;
     g_sim                    : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr             : NATURAL := 0;
@@ -404,7 +402,6 @@ BEGIN
   u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
   GENERIC MAP (
     g_sim                => g_sim,
-    g_technology         => g_technology,
     g_design_name        => g_design_name,
     g_design_note        => g_design_note,
     g_stamp_date         => g_stamp_date,
@@ -685,7 +682,6 @@ BEGIN
   -----------------------------------------------------------------------------
   u_ait: ENTITY lofar2_unb2b_adc_lib.node_adc_input_and_timing
   GENERIC MAP(
-    g_technology                => g_technology,
     g_nof_streams               => c_sdp_S_pn,
     g_buf_nof_data              => c_sdp_V_si_db,
     g_sim                       => g_sim                
@@ -957,7 +953,6 @@ BEGIN
     ---------
     u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
     GENERIC MAP (
-      g_technology => g_technology
     )
     PORT MAP (
       refclk_644 => SA_CLK,
@@ -974,7 +969,6 @@ BEGIN
     ---------------
     u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
     GENERIC MAP (
-      g_technology    => g_technology,
       g_sim           => g_sim,
       g_sim_level     => 1,
       g_nof_macs      => c_nof_10GbE_offload_streams,

applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams and FSUB
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams and FSUB
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd

@@ -26,13 +26,12 @@
 --   Unb2b version for lab testing
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_network_layers_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
@@ -46,7 +45,6 @@ ENTITY lofar2_unb2b_filterbank IS
   GENERIC (
     g_design_name            : STRING  := "lofar2_unb2b_filterbank";
     g_design_note            : STRING  := "UNUSED";
-    g_technology             : NATURAL := c_tech_arria10_e1sg;
     g_buf_nof_data           : NATURAL := 1024;
     g_sim                    : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr             : NATURAL := 0;
@@ -308,7 +306,6 @@ BEGIN
   u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
   GENERIC MAP (
     g_sim                     => g_sim,
-    g_technology              => g_technology,
     g_design_name             => g_design_name,
     g_design_note             => g_design_note,
     g_stamp_date              => g_stamp_date,
@@ -583,7 +580,6 @@ BEGIN
   
   u_ait: ENTITY lofar2_unb2b_adc_lib.node_adc_input_and_timing
   GENERIC MAP(
-    g_technology                => g_technology,
     g_nof_streams               => c_sdp_S_pn,
     g_buf_nof_data              => c_sdp_V_si_db,
     g_sim                       => g_sim                

applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd

@@ -26,12 +26,11 @@
 --   Contains complete ring design with all 8 lanes. 
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd

@@ -29,12 +29,11 @@
 --   However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd

@@ -26,14 +26,13 @@
 --   Unb2b version for lab testing, see https://support.astron.nl/confluence/x/jyu7Ag.
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_network_layers_pkg.ALL;
 USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
@@ -49,7 +48,6 @@ ENTITY lofar2_unb2b_ring IS
   GENERIC (
     g_design_name            : STRING  := "lofar2_unb2b_ring";
     g_design_note            : STRING  := "UNUSED";
-    g_technology             : NATURAL := c_tech_arria10_e1sg;
     g_sim                    : BOOLEAN := FALSE; --Overridden by TB
     g_sim_sync_timeout       : NATURAL := c_sdp_sim.sync_timeout;
     g_sim_unb_nr             : NATURAL := c_sdp_sim.unb_nr;
@@ -356,7 +354,6 @@ BEGIN
   u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
   GENERIC MAP (
     g_sim                     => g_sim,
-    g_technology              => g_technology,
     g_design_name             => g_design_name,
     g_design_note             => g_design_note,
     g_stamp_date              => g_stamp_date,
@@ -951,9 +948,6 @@ BEGIN
   -- PLL
   ---------
   u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
-  GENERIC MAP (
-    g_technology => g_technology
-  )
   PORT MAP (
     refclk_644 => SA_CLK,
     rst_in     => mm_rst,

applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd

@@ -105,7 +105,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
 
   -- Tb
   SIGNAL sim_done            : STD_LOGIC := '0';
-  SIGNAL tb_clk              : STD_LOGIC := '0';  
+  SIGNAL tb_clk              : STD_LOGIC := '0';
+  SIGNAL i_tb_end            : STD_LOGIC := '0';
   SIGNAL rd_data             : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
 
   SIGNAL i_QSFP_0_TX         : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -142,9 +143,12 @@ BEGIN
   ----------------------------------------------------------------------------
   -- System setup
   ----------------------------------------------------------------------------
-  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
-  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
-  SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+  tb_clk <= NOT tb_clk OR i_tb_end AFTER c_tb_clk_period/2;  -- Testbench MM clock
+
+  ext_clk <= NOT ext_clk OR i_tb_end AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk OR i_tb_end AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  SA_CLK <= NOT SA_CLK OR i_tb_end AFTER c_sa_clk_period/2;  -- Serial Gigabit IO sa clock (644 MHz)
+
   pps_rst <= '0' AFTER c_ext_clk_period*2;
 
   INTA <= 'H';  -- pull up
@@ -184,7 +188,7 @@ BEGIN
   
       -- Others
       VERSION      => c_version,
-      ID           => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2c_board_nof_chip_w) ),
+      ID           => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2b_board_nof_chip_w) ),
       TESTIO       => open,
 
       -- I2C Interface to Sensors
@@ -232,8 +236,6 @@ BEGIN
   ------------------------------------------------------------------------------
   -- MM peripeheral accesses via file IO
   ------------------------------------------------------------------------------
-  tb_clk  <= NOT tb_clk AFTER c_tb_clk_period/2;    -- Testbench MM clock
-  
   p_mm_stimuli : PROCESS
   BEGIN
     -- Wait for DUT power up after reset
@@ -374,8 +376,9 @@ BEGIN
     ---------------------------------------------------------------------------   
     sim_done <= '1';
     proc_common_wait_some_cycles(ext_clk, 100);
-    proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
+    proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, i_tb_end);
     WAIT;
   END PROCESS;
 
+  tb_end <= i_tb_end;
 END tb;

applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd

@@ -25,6 +25,7 @@
 -- Usage:
 -- > as 3
 -- > run -all
+--   . tb takes about 1h4m
 -------------------------------------------------------------------------------
 
 LIBRARY IEEE, common_lib;

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams, FSUB and BF
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd

@@ -26,12 +26,11 @@
 --   Contains complete AIT input stage with 12 ADC streams and FSUB
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd

@@ -26,12 +26,11 @@
 --   Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;