diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 80a9ef2e5b4f2ae7c04c209cda350c096c01b289..72449ca9a108e2bd8f0c8d87400706e930e4f18f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 6289c73f28f7bd582e4b3493277575dd6341fa29..1d6bae012f353dc44765c3460a35ceac81031cb7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 0992d5502238a45f1a2a5cf989d91d22fe51d272..4b919d2f04d7766c624beadffdfd2433718ddf13 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -26,12 +26,11 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 1 ADC stream
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index 7ea39b8512ee0fe70ff874ee345277a1ef339513..6314a102a25b56b95cdaf3b69bdb1893843487b5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -26,12 +26,11 @@
-- Unb2b version for lab testing
-- Use revisions to select one_node or full versions
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -43,7 +42,6 @@ ENTITY lofar2_unb2b_adc IS
g_design_name : STRING := "lofar2_unb2b_adc";
g_design_note : STRING := "UNUSED";
g_jesd_freq : STRING := "200MHz";
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := 1024;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
@@ -238,7 +236,6 @@ BEGIN
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -449,7 +446,6 @@ BEGIN
u_ait: ENTITY work.node_adc_input_and_timing
GENERIC MAP(
- g_technology => g_technology,
g_nof_streams => c_nof_streams,
g_jesd_freq => g_jesd_freq,
g_sim => g_sim
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 77501b43b2fd78bdc0690189682e352ae11ff8c6..99a50d0c52259b3ca4f2a7a334dab35d3d7c04b7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -26,12 +26,11 @@
-- Contains all the signal processing blocks to receive and time the ADC input data
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -41,7 +40,6 @@ USE lofar2_sdp_lib.sdp_pkg.ALL;
ENTITY node_adc_input_and_timing IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_jesd_freq : STRING := "200MHz";
g_buf_nof_data : NATURAL := 131072; --8192; --1024;
g_nof_streams : NATURAL := 12;
@@ -452,7 +450,6 @@ BEGIN
u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
- g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_data_w => c_data_w,
g_buf_nof_data => g_buf_nof_data,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index f81831264c54622703af2c96fabe1c164ced74af..b3db26701f2654d8683ee3d395afbcc755b760ad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index b543da94832479e51499a57d5fcbe6974a8c86dc..42036ccb4798049f0c513f8b44f05b58a3dda61a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF with a DP_clk of 256MHz
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index fc365f01a7ca758d8e99db92dfb9e4c9ca122a11..be80697e171af196c5f06ab2b7e2de0ed8347b6c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -26,14 +26,13 @@
-- Unb2b version for lab testing
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -46,7 +45,6 @@ ENTITY lofar2_unb2b_beamformer IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_beamformer";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := 1024;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
@@ -404,7 +402,6 @@ BEGIN
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -685,7 +682,6 @@ BEGIN
-----------------------------------------------------------------------------
u_ait: ENTITY lofar2_unb2b_adc_lib.node_adc_input_and_timing
GENERIC MAP(
- g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
g_buf_nof_data => c_sdp_V_si_db,
g_sim => g_sim
@@ -957,7 +953,6 @@ BEGIN
---------
u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
GENERIC MAP (
- g_technology => g_technology
)
PORT MAP (
refclk_644 => SA_CLK,
@@ -974,7 +969,6 @@ BEGIN
---------------
u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
GENERIC MAP (
- g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => c_nof_10GbE_offload_streams,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index 2a036bf11822b0f99369fe3c5c21b3305b1f4f8d..04516b864886618494c393f780a798e386627d28 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index 1d03769ef47980424a261b5be7e004fb74d2de82..13d1635793d3e78c966148b896db9a661a2852e5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index cc013d2f75c46079af825d5facdd4a7f7eab65d5..41380abcbf75a91f6491c88f9b70bb225a613105 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -26,13 +26,12 @@
-- Unb2b version for lab testing
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -46,7 +45,6 @@ ENTITY lofar2_unb2b_filterbank IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_filterbank";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := 1024;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
@@ -308,7 +306,6 @@ BEGIN
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -583,7 +580,6 @@ BEGIN
u_ait: ENTITY lofar2_unb2b_adc_lib.node_adc_input_and_timing
GENERIC MAP(
- g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
g_buf_nof_data => c_sdp_V_si_db,
g_sim => g_sim
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index f8bf762841a19cd05b0abd6f2b4bba258061acd0..7fc76ed6696dcdfb20f5f62774c4880e4072fe30 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete ring design with all 8 lanes.
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index 2fad382539de10c0df977920b185f23998e50581..a8c3f0a0168862289c1fa9bbb8b6002074f0131b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -29,12 +29,11 @@
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index d973d94e1f5cc283462efc5533e5a15cd578eabc..8d69605e8dea2e6d33de389dbcc854503753b70f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -26,14 +26,13 @@
-- Unb2b version for lab testing, see https://support.astron.nl/confluence/x/jyu7Ag.
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -49,7 +48,6 @@ ENTITY lofar2_unb2b_ring IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_ring";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_sync_timeout : NATURAL := c_sdp_sim.sync_timeout;
g_sim_unb_nr : NATURAL := c_sdp_sim.unb_nr;
@@ -356,7 +354,6 @@ BEGIN
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -951,9 +948,6 @@ BEGIN
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => g_technology
- )
PORT MAP (
refclk_644 => SA_CLK,
rst_in => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index 6bb9e79c3702b2055020ac2a6bb4f4c39e6efa98..39674944233af5cbf6209bccf971009d597bd083 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -105,7 +105,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
-- Tb
SIGNAL sim_done : STD_LOGIC := '0';
- SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL i_tb_end : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
SIGNAL i_QSFP_0_TX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -142,9 +143,12 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ tb_clk <= NOT tb_clk OR i_tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ ext_clk <= NOT ext_clk OR i_tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk OR i_tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK OR i_tb_end AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+
pps_rst <= '0' AFTER c_ext_clk_period*2;
INTA <= 'H'; -- pull up
@@ -184,7 +188,7 @@ BEGIN
-- Others
VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2c_board_nof_chip_w) ),
+ ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2b_board_nof_chip_w) ),
TESTIO => open,
-- I2C Interface to Sensors
@@ -232,8 +236,6 @@ BEGIN
------------------------------------------------------------------------------
-- MM peripeheral accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
-
p_mm_stimuli : PROCESS
BEGIN
-- Wait for DUT power up after reset
@@ -374,8 +376,9 @@ BEGIN
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
+ proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, i_tb_end);
WAIT;
END PROCESS;
+ tb_end <= i_tb_end;
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d5e25f46a925c27a5fd684ae70a471deda6bb66b..8b0daf1ad71c2e3f304eb59254ef14d156b03d44 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -25,6 +25,7 @@
-- Usage:
-- > as 3
-- > run -all
+-- . tb takes about 1h4m
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index 5a5adb2459251d19293075ef2024142788c209e2..6a4e01374b8a536cabe35cbfe7aafb0889af6498 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index 9809ccd9d64421697b336b825ad36d37474763d1..89cac132b07398881c9cfb75052bf47a2baf0ce6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index 545df7db360be7e6787bb639547087862ed88bbe..0d50dc4de8e2f48f9f59c97f67ce5231857c480d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index e89d875b7b5b62e35fc228473a088f0da4017afd..027fe258bc6f957f43bdbd854b68d5e121c73d76 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index 9b7c7ae3d0e55821d966ba9473b214ea0407fde2..d7ec8ed893b10765317e4b837ce9a4e66c0f1880 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -26,12 +26,11 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index c37c83005d6ed1e88cb54a27c067be7caa311515..af05918f96fd4cf5d08b036226baa7b3c94dc1aa 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index 459691bf4d1925cd90f4abf3c6c7f756bbe46fac..eee77b45e1e4c76ea037fd4195c4d0b102a8b67e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -26,12 +26,11 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB with ring
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 3e7aea525e5bd1afc6569562ad4ed14aab8d3619..ed8aa99838b2caecf441bcca6ed632ee80d56b38 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -26,14 +26,13 @@
-- Unb2b version for lab testing, using generic sdp_station.vhd for LOFAR2 SDP application.
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -48,7 +47,6 @@ ENTITY lofar2_unb2b_sdp_station IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_sdp_station";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -492,7 +490,6 @@ BEGIN
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -806,7 +803,6 @@ BEGIN
-----------------------------------------------------------------------------
u_sdp_station : ENTITY lofar2_sdp_lib.sdp_station
GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
g_sim => g_sim,
g_wpfb => g_wpfb,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index d747f8d27fbbe26aca0d6baa7e251895c00477e6..8b90ec994a97b6f6bfccc525e9895f313b0ed6b6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index d234fc5150607d5df051e12290f6e8dded230334..03352e5eb935d33326fc3e2fecfb80637c991e14 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index b27a6f16804f990a2abc76dbf98166ca1637369a..ccbb96fee07935c7e63676922d66c66db7fd7a53 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -26,12 +26,11 @@
-- Unb2b version for lab testing
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE unb2c_board_lib.unb2c_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -44,7 +43,6 @@ ENTITY lofar2_unb2c_filterbank IS
GENERIC (
g_design_name : STRING := "lofar2_unb2c_filterbank";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e2sg;
g_buf_nof_data : NATURAL := 1024;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
@@ -267,7 +265,6 @@ BEGIN
u_ctrl : ENTITY unb2c_board_lib.ctrl_unb2c_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -490,7 +487,6 @@ BEGIN
u_ait: ENTITY lofar2_sdp_lib.node_adc_input_and_timing
GENERIC MAP(
- g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
g_sim => g_sim
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index 472959119f0e4aeb3d9e518ca4d933e240bb261a..6e66921b5b64c0e0d0ca3eea8bd08365e3b5921a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete ring design with all 8 lanes.
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index 15cde745817eb032f408751d2d804e1634a8b393..0b98d35b8f5ed798ab6e22e5085dbb98aa03afa7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -29,12 +29,11 @@
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index af7bae2dc1b9f67c5d5f411b80a32052b2d52260..ef5867134bb4f7251ee7b4fb0a0ae828cac3bdb4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -26,14 +26,13 @@
-- Unb2b version for lab testing, see https://support.astron.nl/confluence/x/jyu7Ag.
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE unb2c_board_lib.unb2c_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -49,7 +48,6 @@ ENTITY lofar2_unb2c_ring IS
GENERIC (
g_design_name : STRING := "lofar2_unb2c_ring";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e2sg;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_sync_timeout : NATURAL := c_sdp_sim.sync_timeout;
g_sim_unb_nr : NATURAL := c_sdp_sim.unb_nr;
@@ -340,7 +338,6 @@ BEGIN
u_ctrl : ENTITY unb2c_board_lib.ctrl_unb2c_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -917,9 +914,6 @@ BEGIN
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => g_technology
- )
PORT MAP (
refclk_644 => SA_CLK,
rst_in => mm_rst,
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index d60ed37ca75f2da0a2607b7f894c0b41f97e67f7..7402bfc69a97c4fd98dd526569744ad73546159e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -106,6 +106,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ring IS
-- Tb
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL i_tb_end : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
SIGNAL i_QSFP_0_TX : t_unb2c_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -142,10 +143,13 @@ BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
- ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
- pps_rst <= '0' AFTER c_ext_clk_period*2;
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ ext_clk <= NOT ext_clk OR i_tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk(0) <= NOT eth_clk(0) OR i_tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK OR i_tb_end AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+
+ pps_rst <= '0' AFTER c_ext_clk_period*2;
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -224,8 +228,6 @@ BEGIN
------------------------------------------------------------------------------
-- MM peripeheral accesses via file IO
------------------------------------------------------------------------------
- tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
-
p_mm_stimuli : PROCESS
BEGIN
-- Wait for DUT power up after reset
@@ -366,8 +368,9 @@ BEGIN
---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, tb_end);
+ proc_common_stop_simulation(NOT g_multi_tb, ext_clk, sim_done, i_tb_end);
WAIT;
END PROCESS;
+ tb_end <= i_tb_end;
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 657aaf6e55d4dfbee633e5098e024bc3b280f271..989e7fdd30cecc03e18f20e4100256a369e8f7d8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -25,6 +25,7 @@
-- Usage:
-- > as 3
-- > run -all
+-- . tb takes about 1h4m
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index 47560a641f9d58d56f1ca6b485baeea043c49507..6d5ace2b2576f1e6995afde43f1ed1b2b7d546d2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 5dc6678c91cbef092d6bf4d2dabb207d27344f0e..7bb426113ce2b13cba8ed6bad0222e095f2d40b3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index e9e12923f78e08e5ae5f69ab6e74167a3c863a92..bd68b32e6ab8237223f6cf1e9c78841fe8317e76 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index fa5338577b612ae8f9b36c7f38f63405d76b5b59..48e097883d58694200d51496e00203bd9b6a7790 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index f5650bac12b1297127d39c624d1a4f2fbb3b60f6..a0258a1d9ca2e00b6e4a46ad88adbc38e7ccc70c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index a902096026e6a3c3bba2d3018610dbdb4750e95f..690c1534ab17cbfaf0467632d46bc0212ad54d07 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -26,12 +26,11 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index a315744f94059ba14e6116bd6fb788e92c2afa6f..cd51deb67a78e007c195b99d7adc4e5211787230 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index c221b9e779b74dbf0ef335892450c539a8155274..4313f7fccb6cd8b68d69737709d3c8b3ab3db3a1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -26,12 +26,11 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB with ring.
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index b1aa7701e5f171c6446ab5ac22ca7631626e4ca5..b4b4601ea9be41cef8a0cf7262862d7bc412fe5f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -26,14 +26,13 @@
-- Unb2c version for lab testing, using generic sdp_station.vhd for LOFAR2 SDP application.
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE unb2c_board_lib.unb2c_board_peripherals_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
@@ -48,7 +47,6 @@ ENTITY lofar2_unb2c_sdp_station IS
GENERIC (
g_design_name : STRING := "lofar2_unb2c_sdp_station";
g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e2sg;
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
@@ -477,7 +475,6 @@ BEGIN
u_ctrl : ENTITY unb2c_board_lib.ctrl_unb2c_board
GENERIC MAP (
g_sim => g_sim,
- g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -773,7 +770,6 @@ BEGIN
-----------------------------------------------------------------------------
u_sdp_station : ENTITY lofar2_sdp_lib.sdp_station
GENERIC MAP (
- g_technology => g_technology,
g_sim => g_sim,
g_wpfb => g_wpfb,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 4bca947d2bf3d642596b9b977a21ca0e319f3620..cfa0669c9591a4cf79d57b65f837ba2392b0faf3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -26,20 +26,17 @@
-- Contains all the signal processing blocks to receive and time the ADC input data
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-LIBRARY IEEE, common_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
+LIBRARY IEEE, common_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.sdp_pkg.ALL;
ENTITY node_sdp_adc_input_and_timing IS
GENERIC (
- g_technology : NATURAL := c_tech_select_default;
g_no_jesd : BOOLEAN := FALSE;
g_buf_nof_data : NATURAL := c_sdp_V_si_db;
g_bsn_nof_clk_per_sync : NATURAL := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
@@ -437,7 +434,6 @@ BEGIN
u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
- g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
g_data_w => c_sdp_W_adc,
g_buf_nof_data => g_buf_nof_data,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 66a11b4e304f6867f5a6ecc7b256b317515d3117..7396bd3d3a6133dab982e8af25078f0f2114b1a7 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -26,14 +26,13 @@
-- Combines sdp nodes. Contains the UniBoard2 HW version independent LOFAR2 SDP application code.
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, tech_pll_lib, tr_10gbe_lib, nw_10gbe_lib, eth_lib, ring_lib;
+LIBRARY IEEE, common_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, tech_pll_lib, tr_10gbe_lib, nw_10gbe_lib, eth_lib, ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
@@ -43,7 +42,6 @@ USE ring_lib.ring_pkg.ALL;
ENTITY sdp_station IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE; -- Overridden by TB
g_sim_sdp : t_sdp_sim := c_sdp_sim; -- Used when g_sim = TRUE, otherwise use HW defaults
g_sim_sync_timeout : NATURAL := 1024;
@@ -603,7 +601,6 @@ BEGIN
-----------------------------------------------------------------------------
u_ait: ENTITY work.node_sdp_adc_input_and_timing
GENERIC MAP(
- g_technology => g_technology,
g_sim => g_sim,
g_no_jesd => g_no_jesd,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
@@ -1026,7 +1023,6 @@ BEGIN
---------------
u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
GENERIC MAP (
- g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => c_nof_10GbE_offload_streams,
@@ -1319,9 +1315,6 @@ BEGIN
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => g_technology
- )
PORT MAP (
refclk_644 => SA_CLK,
rst_in => mm_rst,
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 2f1b37763ab87fe92d8dcccc35243e9248245f2f..d0e7424ddb952190aa640815238a0bfcd085aef3 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -411,7 +411,7 @@ BEGIN
eth1g_eth0_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
- proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
+ proc_tech_tse_setup(g_technology, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
-- Enable RX
proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index 11f71912060c66fd2d324bd4a0530a103d6b1738..b829f35bcc6b52b8ccdb4cd7b1d89cae9eb43143 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -41,7 +41,7 @@ ENTITY ctrl_unb2b_board IS
----------------------------------------------------------------------------
-- General
----------------------------------------------------------------------------
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 580a5dda6129c73761ce6b602a4555e0f747ddcd..aad5e0f1d0ce3d94013115555ec31b4e7c3175d0 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2b_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_design_name : STRING;
g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y
g_stamp_date : NATURAL := 0;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 9db4496059eaa928afed5c9f0d20ed492f30fdaf..fc97dba36a9b041459404b96d4aca29f10df167f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2b_fpga_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_temp_high : NATURAL := 85
);
PORT (
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index 9d228fbe3103f5a3b7951bf8a57ea0d344b62af1..4629190d3d4baaafca210598011568ea471aecff 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_board_clk125_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_use_clkbuf : BOOLEAN := TRUE;
g_use_fpll : BOOLEAN := FALSE
);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index ebc2bb83203883da147e19b9c8df2b2242e65aae..d64018149c18c115490f6575e6cf19e44f6c3221 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -92,7 +92,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_board_clk200_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_use_clkbuf : BOOLEAN := TRUE;
g_use_fpll : BOOLEAN := FALSE;
g_operation_mode : STRING := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index df7d873de9da1b25bf32953dcc02889ab09a2061..ea6beafdc7810281e433a37091937ac3d7432edc 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2b_board_clk25_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10_e1sg
);
PORT (
arst : IN STD_LOGIC := '0';
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index 5f1062f2c1bcd07856191703bd8d4f974a977f01..eb33d3318ce0aced800e4dbd4d1b9210e7233e45 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -36,7 +36,7 @@ ENTITY unb2b_board_system_info IS
g_fw_version : t_unb2b_board_fw_version := c_unb2b_board_fw_version; -- firmware version x.y (4b.4b)
g_aux : t_c_unb2b_board_aux := c_unb2b_board_aux; -- aux contains the hardware version
g_rom_version: NATURAL := 1;
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10_e1sg
);
PORT (
clk : IN STD_LOGIC;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index f643576f3c16c7b5249a247694ebfbc082ca8036..ea691ef68f04d58fcf088916eaa7350c1997166e 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -32,7 +32,7 @@ ENTITY unb2b_board_10gbe IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e1sg;
g_nof_macs : NATURAL;
g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index ccf97cf6edcd7345fea47e80d8c0b5727798a64b..00560ddb4066b0d731cb160ae08eef419a5f0046 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -41,7 +41,7 @@ ENTITY ctrl_unb2c_board IS
----------------------------------------------------------------------------
-- General
----------------------------------------------------------------------------
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index a08e6abd82a95572f6f8a695bc4c9d847f5b872f..0afe23ce4736d30c9cb0520d508b4fe99cf5fc1b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2c_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_design_name : STRING;
g_fw_version : t_unb2c_board_fw_version := c_unb2c_board_fw_version; -- firmware version x.y
g_stamp_date : NATURAL := 0;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index d4c6adc30d7d44a3b30c0703e58cebaeee452324..0595e17b61e040d6c821a9d8d83226d59d31b00a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -33,7 +33,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2c_fpga_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_temp_high : NATURAL := 100
);
PORT (
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
index 166c8067d2f53d0ad0b0e5639c36266c745df987..d49d0578560e4a6e86f95aa95704928b4955b88a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2c_board_clk125_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_use_clkbuf : BOOLEAN := TRUE;
g_use_fpll : BOOLEAN := FALSE
);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
index 321d833e77a863418fd6045366c081136a56501b..d8120d10113bfe2b99d1bfe22f3da3f4061c4949 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
@@ -92,7 +92,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2c_board_clk200_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_use_clkbuf : BOOLEAN := TRUE;
g_use_fpll : BOOLEAN := FALSE;
g_operation_mode : STRING := "NORMAL"; -- "NORMAL", "NO_COMPENSATION", or "SOURCE_SYNCHRONOUS" --> requires PLL_COMPENSATE assignment to an input pin to compensate for (stratixiv)
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
index a88c25c27de14bdf3167f8e7b584b060d546f70e..4024f69c4e6a770a9bfde9cef8a35741d949664f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2c_board_clk25_pll IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10_e2sg
);
PORT (
arst : IN STD_LOGIC := '0';
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index 6eb4763be5148e45f72bddb26a3a92abda5009fa..4bcc9cc53122eb7816fff45a50dca160633afba1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -36,7 +36,7 @@ ENTITY unb2c_board_system_info IS
g_fw_version : t_unb2c_board_fw_version := c_unb2c_board_fw_version; -- firmware version x.y (4b.4b)
g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux; -- aux contains the hardware version
g_rom_version: NATURAL := 2;
- g_technology : NATURAL := c_tech_arria10
+ g_technology : NATURAL := c_tech_arria10_e2sg
);
PORT (
clk : IN STD_LOGIC;
diff --git a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
index 8f51d06fa42e544f036d970ac57f31e8e35a551d..fbe51d4b39a8c4c0ce9e784b9b07fc196cf5320b 100644
--- a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
@@ -32,7 +32,7 @@ ENTITY unb2c_board_10gbe IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
- g_technology : NATURAL := c_tech_arria10;
+ g_technology : NATURAL := c_tech_arria10_e2sg;
g_nof_macs : NATURAL;
g_use_loopback : BOOLEAN := FALSE;
g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index 8d8d53de9753214944ea94635461f7ceb74862f7..dfa1ca0e17a3fb408f19b49bf17b9238acad23ce 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -72,7 +72,7 @@ ARCHITECTURE str OF tech_10gbase_r IS
BEGIN
- gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_10gbase_r_arria10
GENERIC MAP (g_sim, g_nof_channels)
PORT MAP (tr_ref_clk_644,
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 817998a412ea68a37eaf7a90418a38f8ec19d4fe..567a98e134b5c0c7d3ca1c6beeabefa4e093faec 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -50,7 +50,7 @@ BEGIN
-- ip_arria10
-----------------------------------------------------------------------------
- gen_ip_arria10 : IF g_technology=c_tech_arria10 AND g_clock_net="GLOBAL" GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto AND g_clock_net="GLOBAL" GENERATE
u0 : ip_arria10_clkbuf_global
PORT MAP (
inclk => inclk, -- inclk
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index e27d82cdbaf9e5013e0be3d25f02a29b0c5825c7..d323d663c35d43b088f884fe604a6dd4d1e4c76e 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -86,7 +86,7 @@ BEGIN
phy3_in, phy3_io, phy3_ou);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_ddr_arria10
GENERIC MAP (g_tech_ddr)
PORT MAP (ref_clk, ref_rst,
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index dd42a50691be70cdc5166af700b834427050f20f..0b0d8898b1a8ab529a33d37f390b1173544e65d0 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -199,7 +199,7 @@ PACKAGE BODY tech_ddr_pkg IS
BEGIN
CASE g_technology IS
WHEN c_tech_stratixiv => RETURN g_ddr3; -- unb1
- WHEN c_tech_arria10 => RETURN g_ddr4; -- unb2
+ WHEN c_tech_arria10_proto => RETURN g_ddr4; -- unb2
WHEN c_tech_arria10_e3sge3 => RETURN g_ddr4; -- unb2
WHEN c_tech_arria10_e1sg => RETURN g_ddr4; -- unb2b
WHEN c_tech_arria10_e2sg => RETURN g_ddr4; -- unb2c
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
index c7042228dbe56605b6f61b684f6a7f2e2f835578..8b9f6468859569a741b7c1e5aa0a2a2c55dd95fb 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
@@ -26,7 +26,7 @@
-- The tb is self checking based on that tb_tech_eth_10g is self checking
-- and both tb_tech_eth_10g instances send the same and expect the same.
-- Remarks:
--- . For c_tech_arria10 the test fails when g_nof_10ppm /= 0 (erko, 21 nov 2014)
+-- . For c_tech_arria10_proto the test fails when g_nof_10ppm /= 0 (erko, 21 nov 2014)
-- . For c_tech_stratixiv the test fails when g_nof_10ppm /= 0 (erko, 5 dec 2014)
-- Usage:
-- > as 16
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index 901ffac3b5af74bca9214a5c56658de05a8273cd..e783a5ea941afc4a73a698371f68cc4e1e1532e4 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -181,7 +181,7 @@ BEGIN
);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_eth_10g_arria10
GENERIC MAP (
g_sim => g_sim,
diff --git a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
index 1e5cf5a8703be817b54856775632e1c7dc658000..239beeecb92f6d9e548f9e8b709e424e05b5817a 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
@@ -85,7 +85,7 @@ BEGIN
eth_rx_rst_arr <= rx_rst_arr;
END GENERATE;
- gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg GENERATE
+ gen_clocks_10gbase_r : IF g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg GENERATE
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156);
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index 997612ba611b5575ab2bd8c2e1a29d084a4275c2..179aa1ff4cc2c73789dd245c1e5ef38871766008 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -65,7 +65,7 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fifo_dc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 5aba78979bb35ac2b70cc65d9dca8064553e93b0..58352cd3a6d44119d28b98925d9dff48a8a28a33 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -65,7 +65,7 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fifo_dc_mixed_widths
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 4e95260d01e30f918700c8e5ebcd3a07ddadc44c..2694bc2e8b95d2baaa56cb590d57509abf075d3d 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -63,7 +63,7 @@ BEGIN
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fifo_sc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index b6979cc4953acf47320932b37b43b4c8aa98e2f6..b91e7ee92f51a48fd18ed2595e63346228128711 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -75,7 +75,7 @@ BEGIN
-- Note 1: addr must be 32 bits
-- Note 2: need ports for reset, en4b_addr
-- Note 3: ug_altasmi_parallel.pdf not clear what sce(2 downto 0) is for
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_asmi_parallel
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 5839bf349d3bc1e3b98b8cdcd257903470d6e4dd..0ecf1453f058c22e0009d77d2801a2e0a5f588c3 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -248,7 +248,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_stratixiv then
return 24;
end if;
- if technology = c_tech_arria10 then
+ if technology = c_tech_arria10_proto then
return 32;
end if;
if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg or technology = c_tech_arria10_e2sg then
@@ -261,7 +261,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_stratixiv then
return 24;
end if;
- if technology = c_tech_arria10 then
+ if technology = c_tech_arria10_proto then
return 32;
end if;
if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg or technology = c_tech_arria10_e2sg then
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 5d668f11b5f3736201047ff8e1ae2879a11264a9..e30a5affdb1aaabf0a90da230e54e3f9efe23928 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -65,7 +65,7 @@ BEGIN
-- note 1: data_in and data_out must increase to 32 bits
-- note 2: EPCQ-L1024 not yet supported in IP editor
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_remote_update
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 4708a815962e70c0d10ee333725c0521e20b7c3b..446ece63fad87e069e296a2fd51d155492cf194c 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -49,7 +49,7 @@ ARCHITECTURE str OF tech_fpga_temp_sens IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_temp_sense
PORT MAP (
corectl => corectl, -- corectl.corectl
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index e67b45a3998f9ab586e74cf51fbfb60eaf6787f9..670ac1064ada896cf9501f14a2944e4754cc70d4 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -57,7 +57,7 @@ ARCHITECTURE str OF tech_fpga_voltage_sens IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_voltage_sense
PORT MAP (
clock_clk => clock_clk,
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 416cfaad64cfd79615660293912ecc575f404b58..5b38f8b5c988b93616aa60cd1c3272db342ff858 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -50,7 +50,7 @@ ARCHITECTURE str OF tech_fractional_pll_clk125 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fractional_pll_clk125
PORT MAP (
outclk0 => c0, -- outclk0.clk
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 93a08d7957f73671a91d1df73312865086b53a3b..aed39a9266a612d0fcd26dbdaf89c2212398266f 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -49,7 +49,7 @@ ARCHITECTURE str OF tech_fractional_pll_clk200 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fractional_pll_clk200
PORT MAP (
outclk0 => c0, -- outclk0.clk
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 75a38114590dedfdb33605d18b2a337fed584986..4222dd7683f25db8af8202e4d609c547c8eb0afa 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -58,7 +58,7 @@ BEGIN
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ddio_in
GENERIC MAP (g_width)
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 1547d4bd2c1386819e4209b9f4e8869f515fc6e4..fbfe0ce3f31af934353136003bfcbe7522098ad1 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -58,7 +58,7 @@ BEGIN
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ddio_out
GENERIC MAP (g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
diff --git a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
index 9c2474c77330ef24017509c9734273de89a4f703..2b52096438579180952ae2466c2b0435169312e0 100644
--- a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
+++ b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
--- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10
+-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_proto
-- Description
--
-- The clocks come from an external central fPLL:
@@ -193,7 +193,7 @@ BEGIN
u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
GENERIC MAP (
- g_technology => c_tech_arria10,
+ g_technology => c_tech_arria10_proto,
g_pre_header_padding => g_pre_header_padding
)
PORT MAP (
@@ -227,7 +227,7 @@ BEGIN
u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
GENERIC MAP (
- g_technology => c_tech_arria10,
+ g_technology => c_tech_arria10_proto,
g_sim => g_sim,
g_sim_level => g_sim_level,
g_nof_channels => g_nof_channels
@@ -290,7 +290,7 @@ BEGIN
u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10_proto)
)
PORT MAP (
mosi => mac_mosi,
diff --git a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
index c840de488e2342ffa58f0be21fbffab03f91257e..a3af9d8892acd71132a8e727d39a44050b113efc 100644
--- a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
@@ -310,7 +310,7 @@ BEGIN
u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10_e1sg)
)
PORT MAP (
mosi => mac_mosi,
diff --git a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
index 85914052e686eabfef3bed39a8870ac6b0e50617..cdb3620492abf7f80d5e4b6b0664812173f5c817 100644
--- a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
@@ -310,7 +310,7 @@ BEGIN
u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10_e2sg)
)
PORT MAP (
mosi => mac_mosi,
diff --git a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
index c1e19809c2116bd83cd976fb2744d3662944bea8..0ea7f65859e5cc9e7455b3e071b452f11c5b1216 100644
--- a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
@@ -300,7 +300,7 @@ BEGIN
u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10_e3sge3)
)
PORT MAP (
mosi => mac_mosi,
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
index af2746fccf39d12a489242ea72f94aca0da275fc..154fc42ac5e137996d8743080fca0a366a554919 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
@@ -127,7 +127,7 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
- WHEN c_tech_arria10 => proc_tech_mac_10g_setup_arria10( src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
+ WHEN c_tech_arria10_proto => proc_tech_mac_10g_setup_arria10( src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
WHEN OTHERS => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_mac_10g_setup;
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 8a5cf23b6863e9656130411d82c58ef09211c58c..52591a737e6644cf1763228cfe8d8ec37871e565 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -118,8 +118,8 @@ END tech_mac_10g;
ARCHITECTURE str OF tech_mac_10g IS
-- Adapt ST ready latency 1 to IP ready latency
- CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
- CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
+ CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
+ CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
SIGNAL tx_mac_snk_in_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL tx_mac_snk_in : t_dp_sosi;
@@ -153,7 +153,7 @@ BEGIN
xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_mac_10g_arria10
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
index b91cbb6a470e08946216fd768b6a5e2d753919a7..66d4f1f7fd0ad26ffec79596c6afff309f6370e3 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
@@ -63,7 +63,7 @@ END tech_mac_10g_arria10;
ARCHITECTURE str OF tech_mac_10g_arria10 IS
- CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10); -- = 13
+ CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10_proto); -- = 13
SIGNAL mm_rst_n : STD_LOGIC;
SIGNAL tx_rst_n : STD_LOGIC;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index 2acea7c3c25f19121043b8f93f1cab9106542cb6..9583c3522c493f8464939e0668f6b015065cb8cc 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -63,7 +63,7 @@ END tech_mac_10g_arria10_e1sg;
ARCHITECTURE str OF tech_mac_10g_arria10_e1sg IS
- CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10); -- = 13
+ CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10_e1sg); -- = 13
SIGNAL mm_rst_n : STD_LOGIC;
SIGNAL tx_rst_n : STD_LOGIC;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
index f7a598b09f70b591d1df86710e3bfb7619cf30d9..aa139fa18a37e8c2a24eeab40c037a4dd5b9c19a 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
@@ -63,7 +63,7 @@ END tech_mac_10g_arria10_e2sg;
ARCHITECTURE str OF tech_mac_10g_arria10_e2sg IS
- CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10); -- = 13
+ CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10_e2sg); -- = 13
SIGNAL mm_rst_n : STD_LOGIC;
SIGNAL tx_rst_n : STD_LOGIC;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd
index ae3eb9657aba055fa36401bfc72b2b97d53a3893..6327dad72ca81220d676b6c85c1f6fc5b52c8295 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd
@@ -63,7 +63,7 @@ END tech_mac_10g_arria10_e3sge3;
ARCHITECTURE str OF tech_mac_10g_arria10_e3sge3 IS
- CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10); -- = 13
+ CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10_e3sge3); -- = 13
SIGNAL mm_rst_n : STD_LOGIC;
SIGNAL tx_rst_n : STD_LOGIC;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index fe4e87ff6f7bada17431e5bd4c1d056c42ec01da..2455289038abd04dbe8db97cc146fd94713f397e 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -300,13 +300,13 @@ PACKAGE BODY tech_mac_10g_component_pkg IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => v_csr_addr_w := 13;
- WHEN c_tech_arria10 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys, 10 without
- WHEN c_tech_arria10_e3sge3 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e3sge3_mac_10g.qsys, 10 without
+ WHEN c_tech_arria10_proto => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys, 10 without
+ WHEN c_tech_arria10_e3sge3 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e3sge3_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e1sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e2sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
WHEN OTHERS => v_csr_addr_w := 13; -- default to c_tech_stratixiv
END CASE;
- RETURN v_csr_addr_w;
+ RETURN v_csr_addr_w;
END func_tech_mac_10g_csr_addr_w;
END tech_mac_10g_component_pkg;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 342a964b8737673050135aec12b66cd544492667..9e0131c566d1f811f904c35f058f2a00baab86ab 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -64,7 +64,7 @@ BEGIN
PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_cr_cw
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 6e43a2d1284c055676f71c34f8dd053971c4f4c0..7421d579f9cac7a909b2fb05d8493a450afba66c 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -71,7 +71,7 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_crw_crw
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 802e6d8e8557b7920c24c7f406b60dbd1125823e..9b88238eea559af1f0fe181a2d2849677a271980 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -73,7 +73,7 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_crwk_crw
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 54203fc4941920ac51f4e3008577d71c9578bc49..b367295b1545c3e511ebbdece74bad91c54249a4 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -61,7 +61,7 @@ BEGIN
PORT MAP (clock, enable, data, rdaddress, wraddress, wren, q);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_r_w
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
PORT MAP (clock, data, rdaddress, wraddress, wren, q);
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 2fadf629885af98854f6bbc378b6b97df3ce9915..76ac8a9c70e007932448069186ba25f128390c9a 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -57,7 +57,7 @@ BEGIN
PORT MAP (address, clock, clken, q);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
-- use ip_arria10_ram_r_w as ROM
u0 : ip_arria10_ram_r_w
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 81cf3f0459c271f926837c3f13515666e53072f4..1c36a57e133cb754a033aab18d94cdc2b49979b3 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -140,7 +140,7 @@ BEGIN
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
- gen_ip_arria10_ip : IF g_variant="IP" AND g_technology=c_tech_arria10 AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
+ gen_ip_arria10_ip : IF g_variant="IP" AND g_technology=c_tech_arria10_proto AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
@@ -299,7 +299,7 @@ BEGIN
END GENERATE;
-- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl : IF g_variant="RTL" AND (g_technology=c_tech_arria10 OR
+ gen_ip_arria10_rtl : IF g_variant="RTL" AND (g_technology=c_tech_arria10_proto OR
g_technology=c_tech_arria10_e3sge3 OR
g_technology=c_tech_arria10_e1sg OR
g_technology=c_tech_arria10_e2sg) GENERATE
@@ -328,7 +328,7 @@ BEGIN
END GENERATE;
-- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl_canonical : IF g_variant="RTL_C" AND (g_technology=c_tech_arria10 OR
+ gen_ip_arria10_rtl_canonical : IF g_variant="RTL_C" AND (g_technology=c_tech_arria10_proto OR
g_technology=c_tech_arria10_e3sge3 OR
g_technology=c_tech_arria10_e1sg OR
g_technology=c_tech_arria10_e2sg) GENERATE
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 5144eab123dc36ed20aeb369e147568201c1a25a..cb65990aabd3a1ca52cba1c1fe16bcccbffa9a25 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -107,7 +107,7 @@ begin
);
END GENERATE;
- gen_ip_arria10_ip : IF ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="IP") GENERATE
+ gen_ip_arria10_ip : IF ((g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="IP") GENERATE
u0 : ip_arria10_mult
GENERIC MAP(
g_in_a_w => g_in_a_w,
@@ -128,7 +128,7 @@ begin
);
END GENERATE;
- gen_ip_arria10_rtl : IF ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="RTL") GENERATE
+ gen_ip_arria10_rtl : IF ((g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="RTL") GENERATE
u0 : ip_arria10_mult_rtl
GENERIC MAP(
g_in_a_w => g_in_a_w,
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index afe5ff658d8c93d09803f60e9e93b1c4ed1efd83..be4cf0ece34667ca3a324b4c9c8f9ad637ee0ad6 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -50,7 +50,7 @@ ARCHITECTURE str OF tech_pll_clk125 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_clk125
PORT MAP (
rst => areset,
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index ccff2fa603dd3329e2953cc883b9fa28709000d3..f25c4f5052a3f2e9cfce1b0a63f3bb5863fbf33e 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -59,7 +59,7 @@ BEGIN
PORT MAP (areset, inclk0, c0, c1, c2, locked);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_clk200
PORT MAP (
rst => areset,
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 1e2251793d5a83a1fb4afe779ba3aab83c8f770d..d2f4a37419eab1e4d19d693de59c25bc38a54dd2 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -52,7 +52,7 @@ ARCHITECTURE str OF tech_pll_clk25 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_clk25
PORT MAP (
rst => areset,
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 9cee65f0b2671189d6d3d81cccabdcc0843fcbca..1f0bf6459d5c2c5450f85b033d0441bb78daba52 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -70,7 +70,7 @@ ARCHITECTURE str OF tech_pll_xgmii_mac_clocks IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_xgmii_mac_clocks
PORT MAP (
pll_refclk0 => refclk_644,
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index c91c630e2b59c13bdd64599978e87878c79219f8..f913ccfbf032850f4149b1b12cad8acc214fab7d 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -45,7 +45,7 @@ PACKAGE technology_pkg IS
CONSTANT c_tech_stratixiv : INTEGER := 2; -- e.g. used on UniBoard1
CONSTANT c_tech_virtex6 : INTEGER := 3; -- e.g. used on Roach2 for Casper
CONSTANT c_tech_virtex7 : INTEGER := 4; -- e.g. used on Roach3 for Casper
- CONSTANT c_tech_arria10 : INTEGER := 5; -- e.g. used on UniBoard2 first proto (1 board version "00" may 2015)
+ CONSTANT c_tech_arria10_proto : INTEGER := 5; -- e.g. used on UniBoard2 first proto (1 board version "00" may 2015)
CONSTANT c_tech_arria10_e3sge3 : INTEGER := 6; -- e.g. used on UniBoard2 second run (7 boards version "01" dec 2015)
CONSTANT c_tech_arria10_e1sg : INTEGER := 7; -- e.g. used on UniBoard2b third run (5 ARTS boards version "01" feb 2017)
CONSTANT c_tech_arria10_e2sg : INTEGER := 8; -- e.g. used on UniBoard2c (2 LOFAR2.0 SDP boards version "11" f 2021)
diff --git a/libraries/technology/technology_select_pkg.vhd b/libraries/technology/technology_select_pkg.vhd
index a0f1f68ebf692d648077f036d76af0b70e82b69a..277134226066837465ece762caff74f3f5780c6a 100644
--- a/libraries/technology/technology_select_pkg.vhd
+++ b/libraries/technology/technology_select_pkg.vhd
@@ -31,8 +31,5 @@ USE work.technology_pkg.ALL;
PACKAGE technology_select_pkg IS
CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e1sg;
END technology_select_pkg;
diff --git a/libraries/technology/technology_select_pkg_unb1.vhd b/libraries/technology/technology_select_pkg_unb1.vhd
index 430ecaccbc3629c453c7658bcaf3c4a0efb83583..277134226066837465ece762caff74f3f5780c6a 100644
--- a/libraries/technology/technology_select_pkg_unb1.vhd
+++ b/libraries/technology/technology_select_pkg_unb1.vhd
@@ -30,9 +30,6 @@ USE work.technology_pkg.ALL;
PACKAGE technology_select_pkg IS
- CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e1sg;
+ CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
END technology_select_pkg;
diff --git a/libraries/technology/technology_select_pkg_unb2b.vhd b/libraries/technology/technology_select_pkg_unb2b.vhd
index c917c75addffbec503cff882baed27ca9a3c529b..ea1dbe677526c2f66fdb91be99ebc786c337eac5 100644
--- a/libraries/technology/technology_select_pkg_unb2b.vhd
+++ b/libraries/technology/technology_select_pkg_unb2b.vhd
@@ -30,9 +30,6 @@ USE work.technology_pkg.ALL;
PACKAGE technology_select_pkg IS
- --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
- CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e1sg;
+ CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e1sg;
END technology_select_pkg;
diff --git a/libraries/technology/technology_select_pkg_unb2c.vhd b/libraries/technology/technology_select_pkg_unb2c.vhd
index 90c39c8ce2d697b0858047605e8fb2d48f33736b..97a93feecc1318d3410349519d3489050de29e89 100644
--- a/libraries/technology/technology_select_pkg_unb2c.vhd
+++ b/libraries/technology/technology_select_pkg_unb2c.vhd
@@ -30,9 +30,6 @@ USE work.technology_pkg.ALL;
PACKAGE technology_select_pkg IS
- --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
- --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
- CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e2sg;
+ CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e2sg;
END technology_select_pkg;
diff --git a/libraries/technology/tse/tb_tech_tse_pkg.vhd b/libraries/technology/tse/tb_tech_tse_pkg.vhd
index 801e1082466eed682da0c135674a34c1ab5c7d82..43c6110b8d7c4950ef1ec1c7c5eff8bd2b689097 100644
--- a/libraries/technology/tse/tb_tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tb_tech_tse_pkg.vhd
@@ -143,11 +143,11 @@ PACKAGE BODY tb_tech_tse_pkg IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
- WHEN c_tech_arria10 => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
+ WHEN c_tech_arria10_proto => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e3sge3 => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e1sg => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e2sg => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
- WHEN OTHERS => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
+ WHEN OTHERS => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_tse_setup;
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 86aa31094c41fcf81259dd8a9bea067ad9832fa0..09cae2c3bc3530eef7a72f8a9746e738da5869f2 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -138,7 +138,7 @@ BEGIN
tse_led);
END GENERATE;
- gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_tse_arria10
GENERIC MAP (g_ETH_PHY)
PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,