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Commit 0d11b566 authored by Reinier van der Walle's avatar Reinier van der Walle
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parent b6f2e558
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1 merge request!119L2SDP-289
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applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+ 1
− 5
View file @ 0d11b566
......@@ -400,8 +400,6 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
-- 10GbE
SIGNAL tr_ref_clk_312 : STD_LOGIC;
SIGNAL tr_ref_clk_156 : STD_LOGIC;
......@@ -873,9 +871,7 @@ BEGIN
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso,
out_crosslets_info => out_crosslets_info
ram_st_xsq_miso => ram_st_xsq_miso
);
END GENERATE;
......
applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+ 85
− 82
View file @ 0d11b566
......@@ -40,16 +40,16 @@ USE work.sdp_pkg.ALL;
ENTITY node_sdp_correlator IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_P_sq : NATURAL := c_sdp_P_sq
--g_offload_time : NATURAL := c_sdp_offload_time
g_P_sq : NATURAL := c_sdp_P_sq;
g_offload_time : NATURAL := c_sdp_offload_time
);
PORT (
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
--xst_udp_sosi : OUT t_dp_sosi;
--xst_udp_siso : IN t_dp_siso;
xst_udp_sosi : OUT t_dp_sosi;
xst_udp_siso : IN t_dp_siso;
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
......@@ -62,14 +62,16 @@ ENTITY node_sdp_correlator IS
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_st_xsq_miso : OUT t_mem_miso;
reg_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_enable_miso : OUT t_mem_miso;
reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_hdr_dat_miso : OUT t_mem_miso;
--sdp_info : IN t_sdp_info;
--gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
--stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
--stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
--stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
);
END node_sdp_correlator;
......@@ -79,16 +81,16 @@ ARCHITECTURE str OF node_sdp_correlator IS
CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
-- CONSTANT c_nof_masters : POSITIVE := 2;
CONSTANT c_nof_masters : POSITIVE := 2;
-- crosslet statistics offload
-- SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
-- SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
-- SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
-- SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
-- SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
-- SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
-- crosslet statistics offload
SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
......@@ -97,6 +99,7 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Requantize 18b to 16b
......@@ -168,7 +171,7 @@ BEGIN
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
out_crosslets_info => out_crosslets_info
out_crosslets_info => crosslets_info
);
---------------------------------------------------------------
......@@ -234,69 +237,69 @@ BEGIN
mm_mosi_arr => crosslets_mosi_arr,
mm_miso_arr => crosslets_miso_arr,
ram_st_xsq_mosi => ram_st_xsq_mosi, --master_mem_mux_mosi,
ram_st_xsq_miso => ram_st_xsq_miso --master_mem_mux_miso
ram_st_xsq_mosi => master_mem_mux_mosi,
ram_st_xsq_miso => master_mem_mux_miso
);
-- ---------------------------------------------------------------
-- -- MM master multiplexer
-- ---------------------------------------------------------------
-- -- Connect 2 mm_masters to the common_mem_mux output
-- master_mosi_arr(0) <= ram_st_bst_mosi; -- MM access via QSYS MM bus
-- ram_st_bst_miso <= master_miso_arr(0);
-- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
-- ram_st_offload_miso <= master_miso_arr(1);
--
-- u_mem_master_mux : ENTITY mm_lib.mm_master_mux
-- GENERIC MAP (
-- g_nof_masters => c_nof_masters,
-- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
-- )
-- PORT MAP (
-- mm_clk => mm_clk,
--
-- master_mosi_arr => master_mosi_arr,
-- master_miso_arr => master_miso_arr,
-- mux_mosi => master_mem_mux_mosi,
-- mux_miso => master_mem_mux_miso
-- );
--
-- ---------------------------------------------------------------
-- -- XST UDP offload
-- ---------------------------------------------------------------
-- u_sdp_bst_udp_offload: ENTITY work.sdp_statistics_offload
-- GENERIC MAP (
-- g_statistics_type => "XST",
-- g_offload_time => g_offload_time,
-- g_beamset_id => g_beamset_id
-- )
-- PORT MAP (
-- mm_clk => mm_clk,
-- mm_rst => mm_rst,
--
-- dp_clk => dp_clk,
-- dp_rst => dp_rst,
--
-- master_mosi => ram_st_offload_mosi,
-- master_miso => ram_st_offload_miso,
--
-- reg_enable_mosi => reg_stat_enable_mosi,
-- reg_enable_miso => reg_stat_enable_miso,
--
-- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
-- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
--
-- sdp_info => sdp_info,
-- gn_index => TO_UINT(gn_id),
--
-- in_sosi => bf_sum_sosi,
-- out_sosi => bst_udp_sosi,
-- out_siso => bst_udp_siso,
--
-- eth_src_mac => stat_eth_src_mac,
-- udp_src_port => stat_udp_src_port,
-- ip_src_addr => stat_ip_src_addr
-- );
---------------------------------------------------------------
-- MM master multiplexer
---------------------------------------------------------------
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_xsq_mosi; -- MM access via QSYS MM bus
ram_st_xsq_miso <= master_miso_arr(0);
master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by UDP offload
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : ENTITY mm_lib.mm_master_mux
GENERIC MAP (
g_nof_masters => c_nof_masters,
g_rd_latency_min => 1 -- read latency of statistics RAM is 1
)
PORT MAP (
mm_clk => mm_clk,
master_mosi_arr => master_mosi_arr,
master_miso_arr => master_miso_arr,
mux_mosi => master_mem_mux_mosi,
mux_miso => master_mem_mux_miso
);
---------------------------------------------------------------
-- XST UDP offload
---------------------------------------------------------------
u_sdp_xst_udp_offload: ENTITY work.sdp_statistics_offload
GENERIC MAP (
g_statistics_type => "XST",
g_offload_time => g_offload_time
)
PORT MAP (
mm_clk => mm_clk,
mm_rst => mm_rst,
dp_clk => dp_clk,
dp_rst => dp_rst,
master_mosi => ram_st_offload_mosi,
master_miso => ram_st_offload_miso,
reg_enable_mosi => reg_stat_enable_mosi,
reg_enable_miso => reg_stat_enable_miso,
reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
sdp_info => sdp_info,
gn_index => TO_UINT(gn_id),
in_sosi => crosslets_sosi_arr(0),
out_sosi => xst_udp_sosi,
out_siso => xst_udp_siso,
eth_src_mac => stat_eth_src_mac,
udp_src_port => stat_udp_src_port,
ip_src_addr => stat_ip_src_addr,
crosslets_info => crosslets_info
);
END str;
applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+ 1
− 1
View file @ 0d11b566
......@@ -299,7 +299,7 @@ BEGIN
u_mem_master_mux : ENTITY mm_lib.mm_master_mux
GENERIC MAP (
g_nof_masters => c_nof_masters,
g_rd_latency_min => 1 -- TODO, make constant and check if value is right
g_rd_latency_min => 1 -- read latency of statistics RAM is 1
)
PORT MAP (
mm_clk => mm_clk,
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+ 7
− 5
View file @ 0d11b566
......@@ -79,6 +79,7 @@ ENTITY sdp_statistics_offload IS
ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
sdp_info : IN t_sdp_info;
subband_calibrated_flag : IN STD_LOGIC := '0';
crosslets_info : IN STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
gn_index : IN NATURAL
);
......@@ -89,15 +90,15 @@ ARCHITECTURE str OF sdp_statistics_offload IS
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_data_size : NATURAL := 2;
CONSTANT c_nof_data_per_step : NATURAL := 2;
CONSTANT c_data_size : NATURAL := sel_a_b(g_statistics_type="XST", 4, 2); -- XST = 4, SST, BST = 2
CONSTANT c_nof_data_per_step : NATURAL := sel_a_b(g_statistics_type="XST", 4, 2); -- XST = 4, SST, BST = 2;
CONSTANT c_step_size : NATURAL := sel_a_b(g_statistics_type="BST", c_data_size,
sel_a_b(g_statistics_type="XST", c_data_size,
c_data_size * c_nof_data_per_step)); -- SST
CONSTANT c_nof_data : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_N_pol * c_sdp_S_sub_bf,
sel_a_b(g_statistics_type="XST", (c_sdp_S_pn * c_sdp_S_pn * c_nof_complex),
sel_a_b(g_statistics_type="XST", (c_sdp_S_pn * c_sdp_S_pn),
c_sdp_N_sub)); -- SST
CONSTANT c_block_size : NATURAL := c_nof_data * c_step_size;
......@@ -147,12 +148,13 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL selected_crosslet : STD_LOGIC_VECTOR(c_sdp_crosslets_index_w-1 DOWNTO 0);
--SIGNAL sdp_data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
bsn_at_sync <= RESIZE_UVEC(in_sosi.bsn, 64) WHEN rising_edge(dp_clk) AND in_sosi.sync = '1';
selected_crosslet <= crosslets_info(c_sdp_crosslets_index_w-1 DOWNTO 0)
-------------------------------------------------------------------------------
-- Assemble offload header info
......@@ -217,7 +219,7 @@ BEGIN
ELSIF g_statistics_type = "BST" THEN
v.data_id := x"0000" & TO_UVEC(c_beamlet_id, 16);
ELSIF g_statistics_type = "XST" THEN
v.data_id := x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
v.data_id := x"0" & "000" & RESIZE_UVEC(selected_crosslet, 9) & TO_UVEC(c_sdp_S_pn * gn_index, 8) & TO_UVEC(r.block_count * c_sdp_P_pn, 8);
ELSE
v.data_id := x"00000000";
END IF;
......
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