Used hdl_config.py with mode=1 to change build_synth_dir key value into...

Used hdl_config.py with mode=1 to change build_synth_dir key value into /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/build for all hdllib.cfg dictionary files.

Used hdl_config.py with mode=1 to change build_synth_dir key value into...
0caeca64 · Eric Kooistra · 87545f70 · 0caeca64 · 0caeca64 · 0caeca64
Commit 0caeca64 authored Jul 22, 2014 by Eric Kooistra
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = technology_lib
 hdl_lib_uses =
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    technology_pkg.vhd

--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = tech_iobuf_lib
 hdl_lib_uses = technology ip_stratixiv
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    tech_iobuf_component_pkg.vhd

--- a/libraries/technology/ip_arria10/hdllib.cfg
+++ b/libraries/technology/ip_arria10/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = ip_arria10_lib
 hdl_lib_uses = technology
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    ip_arria10_ram_crw_crw.vhd

--- a/libraries/technology/ip_stratixiv/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = ip_stratixiv_lib
 hdl_lib_uses = technology numonyx_m25p128
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    ip_stratixiv_ram_crwk_crw.vhd

--- a/libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_gx/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = ip_stratixiv_tse_sgmii_gx_lib
 hdl_lib_uses = technology
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    ip_stratixiv_tse_sgmii_gx.vho

--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = ip_stratixiv_tse_sgmii_lvds_lib
 hdl_lib_uses = common
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    ip_stratixiv_tse_sgmii_lvds.vho

--- a/libraries/technology/ip_virtex4/hdllib.cfg
+++ b/libraries/technology/ip_virtex4/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = ip_virtex4_lib
 hdl_lib_uses = 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =

--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = tech_memory_lib
 hdl_lib_uses = technology ip_stratixiv ip_arria10 ip_virtex4
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    tech_memory_component_pkg.vhd

--- a/libraries/technology/transceiver/hdllib.cfg
+++ b/libraries/technology/transceiver/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = tech_transceiver_lib
 hdl_lib_uses = technology ip_stratixiv common dp
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    tech_transceiver_component_pkg.vhd

--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -3,7 +3,7 @@ hdl_library_clause_name = tech_tse_lib
 hdl_lib_uses = technology ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx common dp
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 synth_files =
    tech_tse_component_pkg.vhd