Used hdl_config.py with mode=1 to change build_synth_dir key value into...

Used hdl_config.py with mode=1 to change build_synth_dir key value into /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/build for all hdllib.cfg dictionary files.

boards/uniboard1/designs/unb1_minimal/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = unb1_minimal_lib
 hdl_lib_uses = common mm i2c unb1_board
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/designs/unb_minimal/build/synth/quartus/sopc_unb_minimal.vhd

boards/uniboard1/libraries/unb1_board/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = unb1_board_lib
 hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/designs/unb_common/../../modules/MegaWizard/pll/clk200_pll.vhd

libraries/base/common/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = common_lib
 hdl_lib_uses = technology tech_memory tech_fifo tech_iobuf tst
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/common/src/vhdl/common_pkg.vhd

libraries/base/diag/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = diag_lib
 hdl_lib_uses = dp common
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/diag/src/vhdl/diag_bypass.vhd

libraries/base/diagnostics/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = diagnostics_lib
 hdl_lib_uses = common dp diag
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/diagnostics/src/vhdl/diagnostics.vhd

libraries/base/dp/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = dp_lib
 hdl_lib_uses = mm common easics
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd

libraries/base/mm/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = mm_lib
 hdl_lib_uses = common
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/mm/src/vhdl/mm_fields.vhd

libraries/base/sens/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = sens_lib
 hdl_lib_uses = common i2c
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/sens/src/vhdl/sens_ctrl.vhd

libraries/base/tst/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = tst_lib
 hdl_lib_uses = 
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/tst/src/vhdl/tst_output.vhd

libraries/base/uth/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = uth_lib
 hdl_lib_uses = common dp easics
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/uth/src/vhdl/uth_pkg.vhd

libraries/external/easics/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = easics_lib
 hdl_lib_uses = 
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D8.vhd

libraries/external/numonyx_m25p128/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = numonyx_m25p128_lib
 hdl_lib_uses = 
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     

libraries/io/epcs/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = epcs_lib
 hdl_lib_uses = common dp tech_flash
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/epcs/src/vhdl/epcs_reg.vhd

libraries/io/eth/hdllib.cfg

@@ -3,8 +3,7 @@ hdl_library_clause_name = eth_lib
 hdl_lib_uses = dp common tech_tse
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
-
+build_synth_dir= $HDL_BUILD_DIR
 synth_files =
     src/vhdl/eth_pkg.vhd
     $UNB/Firmware/modules/tse/src/vhdl/eth_checksum.vhd
@@ -34,3 +33,4 @@ test_bench_files =
     tb/vhdl/tb_eth_udp_offload.vhd
     tb/vhdl/tb_eth_ihl_to_20.vhd
     tb/vhdl/tb_tb_tb_eth_regression.vhd
+

libraries/io/i2c/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = i2c_lib
 hdl_lib_uses = common
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/Lofar/i2c/src/vhdl/i2c_pkg.vhd

libraries/io/ppsh/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = ppsh_lib
 hdl_lib_uses = common
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/ppsh/src/vhdl/ppsh.vhd

libraries/io/remu/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = remu_lib
 hdl_lib_uses = common tech_flash
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/remu/src/vhdl/remu_reg.vhd

libraries/io/tr_nonbonded/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = tr_nonbonded_lib
 hdl_lib_uses = common dp diag diagnostics tech_transceiver
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     $UNB/Firmware/modules/tr_nonbonded/tb/vhdl/serializer.vhd

libraries/technology/fifo/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = tech_fifo_lib
 hdl_lib_uses = technology ip_stratixiv
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     tech_fifo_component_pkg.vhd

libraries/technology/flash/hdllib.cfg

@@ -3,7 +3,7 @@ hdl_library_clause_name = tech_flash_lib
 hdl_lib_uses = technology ip_stratixiv
 
 build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir = 
+build_synth_dir = $HDL_BUILD_DIR
 
 synth_files =
     tech_flash_component_pkg.vhd