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Commit 095d2afa authored by Eric Kooistra's avatar Eric Kooistra
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Renamed ip_stratixiv_hssi_gx_generic.vhd into... 

Renamed ip_stratixiv_hssi_gx_generic.vhd into ip_stratixiv_hssi_gx_32b_generic.vhd. Idem for tx and rx.
parent 0dbec7f5
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libraries/technology/ip_stratixiv/hdllib.cfg
+ 3
− 3
View file @ 095d2afa
...@@ -28,9 +28,9 @@ synth_files = ...@@ -28,9 +28,9 @@ synth_files =
ip_stratixiv_gxb_reconfig_12.vhd ip_stratixiv_gxb_reconfig_12.vhd
ip_stratixiv_gxb_reconfig.vhd ip_stratixiv_gxb_reconfig.vhd
ip_stratixiv_hssi_gx_generic.vhd ip_stratixiv_hssi_gx_32b_generic.vhd
ip_stratixiv_hssi_tx_generic.vhd ip_stratixiv_hssi_tx_32b_generic.vhd
ip_stratixiv_hssi_rx_generic.vhd ip_stratixiv_hssi_rx_32b_generic.vhd
ip_stratixiv_hssi_gx_16b.vhd ip_stratixiv_hssi_gx_16b.vhd
ip_stratixiv_hssi_tx_16b.vhd ip_stratixiv_hssi_tx_16b.vhd
ip_stratixiv_hssi_rx_16b.vhd ip_stratixiv_hssi_rx_16b.vhd
......
libraries/technology/ip_stratixiv/ip_stratixiv_hssi_gx_generic.vhd → libraries/technology/ip_stratixiv/ip_stratixiv_hssi_gx_32b_generic.vhd
+ 16
− 16
View file @ 095d2afa
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- MODULE: alt4gxb -- MODULE: alt4gxb
-- ============================================================ -- ============================================================
-- File Name: ip_stratixiv_hssi_gx.vhd -- File Name: ip_stratixiv_hssi_gx_32b_generic.vhd
-- Megafunction Name(s): -- Megafunction Name(s):
-- alt4gxb -- alt4gxb
-- --
...@@ -47,7 +47,7 @@ ...@@ -47,7 +47,7 @@
LIBRARY technology_lib; LIBRARY technology_lib;
USE technology_lib.technology_pkg.all; -- Provides a function to convert a natural to a Mbps string. USE technology_lib.technology_pkg.all; -- Provides a function to convert a natural to a Mbps string.
ENTITY ip_stratixiv_hssi_gx_alt4gxb_81na IS ENTITY ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na IS
GENERIC GENERIC
( (
g_mbps : NATURAL; -- Used to determine unb_mbps_string and multiplier unb_mult g_mbps : NATURAL; -- Used to determine unb_mbps_string and multiplier unb_mult
...@@ -82,9 +82,9 @@ ...@@ -82,9 +82,9 @@
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0') tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
); );
END ip_stratixiv_hssi_gx_alt4gxb_81na; END ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na;
ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_alt4gxb_81na IS ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na IS
--VARIABLE unb_mbps_string : STRING := "5000 Mbps"; --VARIABLE unb_mbps_string : STRING := "5000 Mbps";
CONSTANT unb_mbps_string : STRING(1 TO 9) := tech_nat_to_mbps_str(g_mbps); CONSTANT unb_mbps_string : STRING(1 TO 9) := tech_nat_to_mbps_str(g_mbps);
...@@ -2064,14 +2064,14 @@ ...@@ -2064,14 +2064,14 @@
txpmareset => tx_analogreset_out(0) txpmareset => tx_analogreset_out(0)
); );
END RTL; --ip_stratixiv_hssi_gx_alt4gxb_81na END RTL; --ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na
--VALID FILE --VALID FILE
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
ENTITY ip_stratixiv_hssi_gx_generic IS ENTITY ip_stratixiv_hssi_gx_32b_generic IS
GENERIC GENERIC
( (
g_mbps : NATURAL; g_mbps : NATURAL;
...@@ -2106,10 +2106,10 @@ ENTITY ip_stratixiv_hssi_gx_generic IS ...@@ -2106,10 +2106,10 @@ ENTITY ip_stratixiv_hssi_gx_generic IS
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
); );
END ip_stratixiv_hssi_gx_generic; END ip_stratixiv_hssi_gx_32b_generic;
ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_generic IS ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_32b_generic IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
...@@ -2126,7 +2126,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_generic IS ...@@ -2126,7 +2126,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_gx_generic IS
COMPONENT ip_stratixiv_hssi_gx_alt4gxb_81na COMPONENT ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na
GENERIC ( GENERIC (
g_mbps : NATURAL; g_mbps : NATURAL;
starting_channel_number : NATURAL starting_channel_number : NATURAL
...@@ -2175,7 +2175,7 @@ BEGIN ...@@ -2175,7 +2175,7 @@ BEGIN
tx_clkout <= sub_wire10(0 DOWNTO 0); tx_clkout <= sub_wire10(0 DOWNTO 0);
tx_dataout <= sub_wire11(0 DOWNTO 0); tx_dataout <= sub_wire11(0 DOWNTO 0);
ip_stratixiv_hssi_gx_alt4gxb_81na_component : ip_stratixiv_hssi_gx_alt4gxb_81na ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na_component : ip_stratixiv_hssi_gx_32b_generic_alt4gxb_81na
GENERIC MAP ( GENERIC MAP (
g_mbps => g_mbps, g_mbps => g_mbps,
starting_channel_number => starting_channel_number starting_channel_number => starting_channel_number
...@@ -2425,10 +2425,10 @@ END RTL; ...@@ -2425,10 +2425,10 @@ END RTL;
-- Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0 -- Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
-- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 -- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 -- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_32b_generic.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_32b_generic.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_32b_generic.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_32b_generic.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_32b_generic.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_gx_32b_generic_inst.vhd FALSE
-- Retrieval info: LIB_FILE: stratixiv_hssi -- Retrieval info: LIB_FILE: stratixiv_hssi
libraries/technology/ip_stratixiv/ip_stratixiv_hssi_rx_generic.vhd → libraries/technology/ip_stratixiv/ip_stratixiv_hssi_rx_32b_generic.vhd
+ 16
− 16
View file @ 095d2afa
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- MODULE: alt4gxb -- MODULE: alt4gxb
-- ============================================================ -- ============================================================
-- File Name: ip_stratixiv_hssi_rx_generic.vhd -- File Name: ip_stratixiv_hssi_rx_32b_generic.vhd
-- Megafunction Name(s): -- Megafunction Name(s):
-- alt4gxb -- alt4gxb
-- --
...@@ -47,7 +47,7 @@ ...@@ -47,7 +47,7 @@
LIBRARY technology_lib; LIBRARY technology_lib;
USE technology_lib.technology_pkg.all; -- Provides a function to convert a natural to a Mbps string. USE technology_lib.technology_pkg.all; -- Provides a function to convert a natural to a Mbps string.
ENTITY ip_stratixiv_hssi_rx_generic_alt4gxb_qi67 IS ENTITY ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67 IS
GENERIC GENERIC
( (
g_mbps : NATURAL; -- Used to determine unb_mbps_string and multiplier unb_mult g_mbps : NATURAL; -- Used to determine unb_mbps_string and multiplier unb_mult
...@@ -74,9 +74,9 @@ ...@@ -74,9 +74,9 @@
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) rx_patterndetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
); );
END ip_stratixiv_hssi_rx_generic_alt4gxb_qi67; END ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67;
ARCHITECTURE RTL OF ip_stratixiv_hssi_rx_generic_alt4gxb_qi67 IS ARCHITECTURE RTL OF ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67 IS
CONSTANT unb_mbps_string : STRING(1 TO 9) := tech_nat_to_mbps_str(g_mbps); CONSTANT unb_mbps_string : STRING(1 TO 9) := tech_nat_to_mbps_str(g_mbps);
CONSTANT unb_mult : NATURAL := (g_mbps*2)/625; -- Workaround (division not possible with non-integers): equals (g_mbps/2)/156.25 CONSTANT unb_mult : NATURAL := (g_mbps*2)/625; -- Workaround (division not possible with non-integers): equals (g_mbps/2)/156.25
...@@ -1406,14 +1406,14 @@ ...@@ -1406,14 +1406,14 @@
testbussel => wire_receive_pma0_testbussel testbussel => wire_receive_pma0_testbussel
); );
END RTL; --ip_stratixiv_hssi_rx_generic_alt4gxb_qi67 END RTL; --ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67
--VALID FILE --VALID FILE
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
ENTITY ip_stratixiv_hssi_rx_generic IS ENTITY ip_stratixiv_hssi_rx_32b_generic IS
GENERIC GENERIC
( (
g_mbps : NATURAL; g_mbps : NATURAL;
...@@ -1440,10 +1440,10 @@ ENTITY ip_stratixiv_hssi_rx_generic IS ...@@ -1440,10 +1440,10 @@ ENTITY ip_stratixiv_hssi_rx_generic IS
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) rx_patterndetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
); );
END ip_stratixiv_hssi_rx_generic; END ip_stratixiv_hssi_rx_32b_generic;
ARCHITECTURE RTL OF ip_stratixiv_hssi_rx_generic IS ARCHITECTURE RTL OF ip_stratixiv_hssi_rx_32b_generic IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
...@@ -1457,7 +1457,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_rx_generic IS ...@@ -1457,7 +1457,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_rx_generic IS
COMPONENT ip_stratixiv_hssi_rx_generic_alt4gxb_qi67 COMPONENT ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67
GENERIC ( GENERIC (
g_mbps : NATURAL; g_mbps : NATURAL;
starting_channel_number : NATURAL starting_channel_number : NATURAL
...@@ -1495,7 +1495,7 @@ BEGIN ...@@ -1495,7 +1495,7 @@ BEGIN
rx_dataout <= sub_wire7(31 DOWNTO 0); rx_dataout <= sub_wire7(31 DOWNTO 0);
rx_errdetect <= sub_wire8(3 DOWNTO 0); rx_errdetect <= sub_wire8(3 DOWNTO 0);
ip_stratixiv_hssi_rx_generic_alt4gxb_qi67_component : ip_stratixiv_hssi_rx_generic_alt4gxb_qi67 ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67_component : ip_stratixiv_hssi_rx_32b_generic_alt4gxb_qi67
GENERIC MAP ( GENERIC MAP (
g_mbps => g_mbps, g_mbps => g_mbps,
...@@ -1684,10 +1684,10 @@ END RTL; ...@@ -1684,10 +1684,10 @@ END RTL;
-- Retrieval info: CONNECT: rx_errdetect 0 0 4 0 @rx_errdetect 0 0 4 0 -- Retrieval info: CONNECT: rx_errdetect 0 0 4 0 @rx_errdetect 0 0 4 0
-- Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0 -- Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
-- Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0 -- Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_generic.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_32b_generic.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_generic.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_32b_generic.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_generic.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_32b_generic.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_generic.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_32b_generic.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_generic.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_32b_generic.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_generic_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_rx_32b_generic_inst.vhd FALSE
-- Retrieval info: LIB_FILE: stratixiv_hssi -- Retrieval info: LIB_FILE: stratixiv_hssi
libraries/technology/ip_stratixiv/ip_stratixiv_hssi_tx_generic.vhd → libraries/technology/ip_stratixiv/ip_stratixiv_hssi_tx_32b_generic.vhd
+ 16
− 16
View file @ 095d2afa
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
-- MODULE: alt4gxb -- MODULE: alt4gxb
-- ============================================================ -- ============================================================
-- File Name: ip_stratixiv_hssi_tx_generic.vhd -- File Name: ip_stratixiv_hssi_tx_32b_generic.vhd
-- Megafunction Name(s): -- Megafunction Name(s):
-- alt4gxb -- alt4gxb
-- --
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
LIBRARY technology_lib; LIBRARY technology_lib;
USE technology_lib.technology_pkg.all; -- Provides a function to convert a natural to a Mbps string. USE technology_lib.technology_pkg.all; -- Provides a function to convert a natural to a Mbps string.
ENTITY ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4 IS ENTITY ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4 IS
GENERIC GENERIC
( (
g_mbps : NATURAL; -- Used to determine unb_mbps_string and multiplier unb_mult g_mbps : NATURAL; -- Used to determine unb_mbps_string and multiplier unb_mult
...@@ -67,9 +67,9 @@ ...@@ -67,9 +67,9 @@
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0') tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
); );
END ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4; END ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4;
ARCHITECTURE RTL OF ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4 IS ARCHITECTURE RTL OF ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4 IS
CONSTANT unb_mbps_string : STRING(1 TO 9) := tech_nat_to_mbps_str(g_mbps); CONSTANT unb_mbps_string : STRING(1 TO 9) := tech_nat_to_mbps_str(g_mbps);
CONSTANT unb_mult : NATURAL := (g_mbps*2)/625; -- Workaround (division not possible with non-integers): equals (g_mbps/2)/156.25 CONSTANT unb_mult : NATURAL := (g_mbps*2)/625; -- Workaround (division not possible with non-integers): equals (g_mbps/2)/156.25
...@@ -1181,14 +1181,14 @@ ...@@ -1181,14 +1181,14 @@
txpmareset => tx_analogreset_out(0) txpmareset => tx_analogreset_out(0)
); );
END RTL; --ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4 END RTL; --ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4
--VALID FILE --VALID FILE
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
ENTITY ip_stratixiv_hssi_tx_generic IS ENTITY ip_stratixiv_hssi_tx_32b_generic IS
GENERIC( GENERIC(
g_mbps : NATURAL g_mbps : NATURAL
); );
...@@ -1205,10 +1205,10 @@ ENTITY ip_stratixiv_hssi_tx_generic IS ...@@ -1205,10 +1205,10 @@ ENTITY ip_stratixiv_hssi_tx_generic IS
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
); );
END ip_stratixiv_hssi_tx_generic; END ip_stratixiv_hssi_tx_32b_generic;
ARCHITECTURE RTL OF ip_stratixiv_hssi_tx_generic IS ARCHITECTURE RTL OF ip_stratixiv_hssi_tx_32b_generic IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
...@@ -1216,7 +1216,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_tx_generic IS ...@@ -1216,7 +1216,7 @@ ARCHITECTURE RTL OF ip_stratixiv_hssi_tx_generic IS
COMPONENT ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4 COMPONENT ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4
GENERIC ( GENERIC (
g_mbps : NATURAL g_mbps : NATURAL
...@@ -1240,7 +1240,7 @@ BEGIN ...@@ -1240,7 +1240,7 @@ BEGIN
tx_clkout <= sub_wire1(0 DOWNTO 0); tx_clkout <= sub_wire1(0 DOWNTO 0);
tx_dataout <= sub_wire2(0 DOWNTO 0); tx_dataout <= sub_wire2(0 DOWNTO 0);
ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4_component : ip_stratixiv_hssi_tx_generic_alt4gxb_dgn4 ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4_component : ip_stratixiv_hssi_tx_32b_generic_alt4gxb_dgn4
GENERIC MAP ( GENERIC MAP (
g_mbps => g_mbps g_mbps => g_mbps
) )
...@@ -1380,10 +1380,10 @@ END RTL; ...@@ -1380,10 +1380,10 @@ END RTL;
-- Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0 -- Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
-- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0 -- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0 -- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_generic.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_32b_generic.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_generic.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_32b_generic.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_generic.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_32b_generic.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_generic.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_32b_generic.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_generic.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_32b_generic.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_generic_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_hssi_tx_32b_generic_inst.vhd FALSE
-- Retrieval info: LIB_FILE: stratixiv_hssi -- Retrieval info: LIB_FILE: stratixiv_hssi
libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+ 3
− 3
View file @ 095d2afa
...@@ -135,7 +135,7 @@ BEGIN ...@@ -135,7 +135,7 @@ BEGIN
gen_tr : IF g_tx = TRUE AND g_rx = TRUE GENERATE --Generate duplex transceivers gen_tr : IF g_tx = TRUE AND g_rx = TRUE GENERATE --Generate duplex transceivers
gen_32b : IF g_data_w = 32 GENERATE gen_32b : IF g_data_w = 32 GENERATE
u_gx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_gx_generic u_gx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_gx_32b_generic
GENERIC MAP ( GENERIC MAP (
g_mbps => g_mbps, g_mbps => g_mbps,
starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
...@@ -225,7 +225,7 @@ BEGIN ...@@ -225,7 +225,7 @@ BEGIN
gen_rx : IF g_tx = FALSE AND g_rx = TRUE GENERATE --Generate receivers only gen_rx : IF g_tx = FALSE AND g_rx = TRUE GENERATE --Generate receivers only
gen_32b : IF g_data_w = 32 GENERATE gen_32b : IF g_data_w = 32 GENERATE
u_rx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_rx_generic u_rx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_rx_32b_generic
GENERIC MAP ( GENERIC MAP (
g_mbps => g_mbps, g_mbps => g_mbps,
starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances starting_channel_number => i*4 --Starting channel numbers must be 0,4,8,12 etc for individual ALTGX instances
...@@ -289,7 +289,7 @@ BEGIN ...@@ -289,7 +289,7 @@ BEGIN
gen_tx : IF g_tx = TRUE AND g_rx = FALSE GENERATE gen_tx : IF g_tx = TRUE AND g_rx = FALSE GENERATE
gen_32b : IF g_data_w = 32 GENERATE gen_32b : IF g_data_w = 32 GENERATE
u_tx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_tx_generic u_tx: ENTITY ip_stratixiv_lib.ip_stratixiv_hssi_tx_32b_generic
GENERIC MAP ( GENERIC MAP (
g_mbps => g_mbps g_mbps => g_mbps
) )
......
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