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Commit 06018018 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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for unb2_minimal

parent eae31116
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boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ 5
− 3
View file @ 06018018
...@@ -56,6 +56,8 @@ set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10 ...@@ -56,6 +56,8 @@ set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}] set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous \ #set_clock_groups -asynchronous \
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \ #-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
...@@ -64,7 +66,7 @@ set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10 ...@@ -64,7 +66,7 @@ set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10
#JTAG Signal Constraints #JTAG Signal Constraints
#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook) #constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook)
set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi] #set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms] #set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo] #set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]
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