From 060180183393dde2008047fe1cbf167371a701c4 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 24 Sep 2015 11:55:53 +0000
Subject: [PATCH] for unb2_minimal
---
.../uniboard2/libraries/unb2_board/quartus/unb2_board.sdc | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
index ea45caa2cc..6d2b54004d 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
@@ -56,6 +56,8 @@ set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous \
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
@@ -64,7 +66,7 @@ set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10
#JTAG Signal Constraints
#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook)
-set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
-set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
-set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]
+#set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
+#set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
+#set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]
--
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