Skip to content
Snippets Groups Projects
Commit 0261b80f authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
Browse files

Reodered ports in the package file. Added Arria 10 to the wrappers

parent 22f4df28
No related branches found
No related tags found
No related merge requests found
...@@ -62,4 +62,12 @@ BEGIN ...@@ -62,4 +62,12 @@ BEGIN
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write); PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write);
END GENERATE; END GENERATE;
-- Note 1: addr must be 32 bits
-- Note 2: need ports for reset, en4b_addr
-- Note 3: ug_altasmi_parallel.pdf not clear what sce(2 downto 0) is for
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_asmi_parallel
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
...@@ -70,23 +70,23 @@ PACKAGE tech_flash_component_pkg IS ...@@ -70,23 +70,23 @@ PACKAGE tech_flash_component_pkg IS
component ip_arria10_asmi_parallel is component ip_arria10_asmi_parallel is
port ( port (
clkin : in std_logic := 'X'; -- clk addr : in std_logic_vector(31 downto 0);
read : in std_logic := 'X'; -- read clkin : in std_logic;
rden : in std_logic := 'X'; -- rden datain : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(31 downto 0) := (others => 'X'); -- addr rden : in std_logic;
reset : in std_logic := 'X'; -- reset read : in std_logic;
sce : in std_logic_vector(2 downto 0) := (others => 'X'); -- sce sector_erase : in std_logic;
dataout : out std_logic_vector(7 downto 0); -- dataout shift_bytes : in std_logic;
busy : out std_logic; -- busy wren : in std_logic;
data_valid : out std_logic; -- data_valid write : in std_logic;
wren : in std_logic := 'X'; -- wren busy : out std_logic;
en4b_addr : in std_logic := 'X'; -- en4b_addr data_valid : out std_logic;
write : in std_logic := 'X'; -- write dataout : out std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain illegal_erase : out std_logic;
illegal_write : out std_logic; -- illegal_write illegal_write : out std_logic;
sector_erase : in std_logic := 'X'; -- sector_erase reset : in std_logic;
illegal_erase : out std_logic; -- illegal_erase sce : in std_logic_vector(2 downto 0);
shift_bytes : in std_logic := 'X' -- shift_bytes en4b_addr : in std_logic
); );
end component ip_arria10_asmi_parallel; end component ip_arria10_asmi_parallel;
...@@ -95,16 +95,16 @@ PACKAGE tech_flash_component_pkg IS ...@@ -95,16 +95,16 @@ PACKAGE tech_flash_component_pkg IS
component ip_arria10_remote_update is component ip_arria10_remote_update is
port ( port (
read_param : in std_logic := 'X'; -- read_param clock : in std_logic;
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param data_in : in std_logic_vector(31 downto 0);
reconfig : in std_logic := 'X'; -- reconfig param : in std_logic_vector(2 downto 0);
reset_timer : in std_logic := 'X'; -- reset_timer read_param : in std_logic;
clock : in std_logic := 'X'; -- clk reconfig : in std_logic;
reset : in std_logic := 'X'; -- reset reset : in std_logic;
busy : out std_logic; -- busy reset_timer : in std_logic;
data_out : out std_logic_vector(31 downto 0); -- data_out write_param : in std_logic;
write_param : in std_logic := 'X'; -- write_param busy : out std_logic;
data_in : in std_logic_vector(31 downto 0) := (others => 'X') -- data_in data_out : out std_logic_vector(31 downto 0)
); );
end component ip_arria10_remote_update; end component ip_arria10_remote_update;
......
...@@ -58,4 +58,11 @@ BEGIN ...@@ -58,4 +58,11 @@ BEGIN
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out); PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE; END GENERATE;
-- note 1: data_in and data_out must increase to 32 bits
-- note 2: EPCQ-L1024 not yet supported in IP editor
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_remote_update
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment