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Commit 01da47df authored by Reinier van der Walle's avatar Reinier van der Walle
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removed hdllib entry of unused TB

parent 53424d47
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2 merge requests!319Resolve HPR-87,!315Resolve HPR-87
Pipeline #46801 passed
Stage: simulation
Stage: synthesis
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libraries/base/axi4/hdllib.cfg
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...@@ -16,7 +16,6 @@ test_bench_files = ...@@ -16,7 +16,6 @@ test_bench_files =
regression_test_vhdl = regression_test_vhdl =
tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
tb/vhdl/tb_axi4_lite_ram.vhd
[modelsim_project_file] [modelsim_project_file]
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