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Resolve HPR-87

Merged Resolve HPR-87
HPR-87 into master
5 unresolved threads
Merged Reinier van der Walle requested to merge HPR-87 into master
5 unresolved threads

Closes HPR-87

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libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd 0 → 100644
28 -------------------------------------------------------------------------------
29
30 LIBRARY IEEE, common_lib;
31 USE IEEE.STD_LOGIC_1164.ALL;
32 USE IEEE.NUMERIC_STD.ALL;
33 USE std.textio.ALL;
34 USE IEEE.STD_LOGIC_TEXTIO.ALL;
35 USE common_lib.common_pkg.ALL;
36 USE common_lib.common_mem_pkg.ALL;
37
38 PACKAGE axi4_lite_pkg IS
39
40 ------------------------------------------------------------------------------
41 -- Simple AXI4 lite memory access (for MM control interface)
42 ------------------------------------------------------------------------------
43 CONSTANT c_max_string : NATURAL := 128;
  • Eric Kooistra
    Eric Kooistra @kooistra started a thread on the diff
    • libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd 0 → 100644
    156 mm_from_axi4_copi.rd <= axi4_in_copi.arvalid;
    157
    158 axi4_in_cipo.awready <= NOT mm_from_axi4_cipo.waitrequest;
    159 axi4_in_cipo.wready <= NOT mm_from_axi4_cipo.waitrequest;
    160 axi4_in_cipo.bresp <= c_axi4_lite_resp_okay;
    161 axi4_in_cipo.bvalid <= q_bvalid;
    162 axi4_in_cipo.arready <= NOT mm_from_axi4_cipo.waitrequest;
    163 axi4_in_cipo.rdata <= mm_from_axi4_cipo.rddata(c_axi4_lite_data_w-1 DOWNTO 0);
    164 axi4_in_cipo.rresp <= c_axi4_lite_resp_okay;
    165 axi4_in_cipo.rvalid <= mm_from_axi4_cipo.rdval;
    166
    167 -- Generate bvalid
    168 q_bvalid <= d_bvalid WHEN rising_edge(in_clk);
    169 p_bvalid : PROCESS(i_rst, mm_from_axi4_cipo, mm_from_axi4_copi, axi4_in_copi)
    170 BEGIN
    171 d_bvalid <= q_bvalid;
  • Eric Kooistra
    Eric Kooistra @kooistra started a thread on an old version of the diff
    • libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd 0 → 100644
    154 mm_from_axi4_copi.wrdata(c_axi4_lite_data_w-1 DOWNTO 0) <= axi4_in_copi.wdata;
    155 mm_from_axi4_copi.wr <= axi4_in_copi.awvalid;
    156 mm_from_axi4_copi.rd <= axi4_in_copi.arvalid;
    157
    158 axi4_in_cipo.awready <= NOT mm_from_axi4_cipo.waitrequest;
    159 axi4_in_cipo.wready <= NOT mm_from_axi4_cipo.waitrequest;
    160 axi4_in_cipo.bresp <= c_axi4_lite_resp_okay;
    161 axi4_in_cipo.bvalid <= q_bvalid;
    162 axi4_in_cipo.arready <= NOT mm_from_axi4_cipo.waitrequest;
    163 axi4_in_cipo.rdata <= mm_from_axi4_cipo.rddata(c_axi4_lite_data_w-1 DOWNTO 0);
    164 axi4_in_cipo.rresp <= c_axi4_lite_resp_okay;
    165 axi4_in_cipo.rvalid <= mm_from_axi4_cipo.rdval;
    166
    167 -- Generate bvalid
    168 q_bvalid <= d_bvalid WHEN rising_edge(in_clk);
    169 p_bvalid : PROCESS(i_rst, mm_from_axi4_cipo, mm_from_axi4_copi, axi4_in_copi)
  • Eric Kooistra
    Eric Kooistra @kooistra started a thread on the diff
    • libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd 0 → 100644
    36 USE dp_lib.dp_stream_pkg.ALL;
    37 USE work.axi4_stream_pkg.ALL;
    38 USE work.axi4_lite_pkg.ALL;
    39
    40 ENTITY axi4_lite_mm_bridge IS
    41 GENERIC (
    42 g_active_low_rst : BOOLEAN := FALSE -- When True, in_rst is interpreted as active-low.
    43 );
    44 PORT (
    45 in_clk : IN STD_LOGIC := '0';
    46 in_rst : IN STD_LOGIC := is_true(g_active_low_rst); -- Default state is "not in reset".
    47
    48 aresetn : OUT STD_LOGIC := '1'; -- AXI4 active-low reset
    49 mm_rst : OUT STD_LOGIC := '0'; -- MM active-high reset
    50
    51 axi4_in_copi : IN t_axi4_lite_copi := c_axi4_lite_copi_rst;
    • Eric Kooistra
      Eric Kooistra @kooistra
      Owner

      Liever volgorde bijvoorbeeld zo en met comment, dus zodanig dat ports volgorde meer de functionaliteit volgt:

          -- Translate AXI4 lite to MM
    axi4_in_copi  : IN  t_axi4_lite_copi := c_axi4_lite_copi_rst;
    axi4_in_cipo  : OUT t_axi4_lite_cipo := c_axi4_lite_cipo_rst;

    mm_out_copi   : OUT t_mem_copi   := c_mem_copi_rst;
    mm_out_cipo   : IN  t_mem_cipo   := c_mem_cipo_rst;

    -- Translate MM to AXI4 lite
    mm_in_copi    : IN  t_mem_copi   := c_mem_copi_rst;
    mm_in_cipo    : OUT t_mem_cipo   := c_mem_cipo_rst;

    axi4_out_copi : OUT t_axi4_lite_copi := c_axi4_lite_copi_rst;
    axi4_out_cipo : IN  t_axi4_lite_cipo := c_axi4_lite_cipo_rst;
      Edited by Eric Kooistra
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  • Eric Kooistra
    Eric Kooistra @kooistra started a thread on an old version of the diff
    • libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd 0 → 100644
    54 axi4_out_copi : OUT t_axi4_lite_copi := c_axi4_lite_copi_rst;
    55 axi4_out_cipo : IN t_axi4_lite_cipo := c_axi4_lite_cipo_rst;
    56
    57 mm_in_copi : IN t_mem_copi := c_mem_copi_rst;
    58 mm_in_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
    59
    60 mm_out_copi : OUT t_mem_copi := c_mem_copi_rst;
    61 mm_out_cipo : IN t_mem_cipo := c_mem_cipo_rst
    62 );
    63 END axi4_lite_mm_bridge;
    64
    65 ARCHITECTURE str OF axi4_lite_mm_bridge IS
    66 -- Sum of all t_mem_copi fields widths (synthesis will optimize away unused address and data bits)
    67 CONSTANT c_data_w : NATURAL := c_mem_address_w + c_mem_data_w + 2; -- 32 + 72 + 1 (wr) + 1 (rd) = 106
    68
    69 SIGNAL i_rst : STD_LOGIC := '0'; -- Internal active high reset.
  • Reinier van der Walle added 1 commit

    added 1 commit

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  • Eric Kooistra mentioned in commit 6a5db5ed

    mentioned in commit 6a5db5ed

  • Eric Kooistra merged

    merged

  • Daniel van der Schuur unassigned @walle

    unassigned @walle

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