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tb_common_toggle_align.vhd

Eric Kooistra authored
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tb_common_toggle_align.vhd 4.95 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2017
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Author: Eric Kooistra, 20 jul 2017, Created
-- Purpose: Test bench for common_toggle_align.vhd
-- Usage:
-- > as 10
-- > run -all
-- Observe out_toggle in Wave Window in relation to in_toggle and align
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE work.common_pkg.ALL;
USE work.tb_common_pkg.ALL;
ENTITY tb_common_toggle_align IS
END tb_common_toggle_align;
ARCHITECTURE tb OF tb_common_toggle_align IS
CONSTANT clk_period : TIME := 10 ns;
CONSTANT c_interval : NATURAL := 10;
CONSTANT c_pipeline : NATURAL := 0;
CONSTANT c_toggle_period : NATURAL := 4;
CONSTANT c_half_period : NATURAL := c_toggle_period/2;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL in_align : STD_LOGIC;
SIGNAL in_toggle : STD_LOGIC;
SIGNAL out_toggle : STD_LOGIC;
BEGIN
clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER 7 * clk_period;
p_in_stimuli : PROCESS
BEGIN
in_align <= '1';
in_toggle <= '0';
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
---------------------------------------------------------------------------
-- align
---------------------------------------------------------------------------
in_align <= '1';
-- start toggling
FOR I IN 0 TO c_interval-1 LOOP
in_toggle <= NOT in_toggle;
proc_common_wait_some_cycles(clk, c_half_period);
END LOOP;
-- introduce a glitch in the toggling and check that out_toggle remains aligned
proc_common_wait_some_cycles(clk, 1);
FOR I IN 0 TO c_interval-1 LOOP
in_toggle <= NOT in_toggle;
proc_common_wait_some_cycles(clk, c_half_period);
END LOOP;
---------------------------------------------------------------------------
-- maintain
---------------------------------------------------------------------------
in_align <= '0';
-- continue toggling
FOR I IN 0 TO c_interval-1 LOOP
in_toggle <= NOT in_toggle;
proc_common_wait_some_cycles(clk, c_half_period);
END LOOP;
-- introduce a glitch in the toggling and check that out_toggle ignores the glitch
proc_common_wait_some_cycles(clk, 1);
FOR I IN 0 TO c_interval-1 LOOP
in_toggle <= NOT in_toggle;
proc_common_wait_some_cycles(clk, c_half_period);
END LOOP;
---------------------------------------------------------------------------
-- align again
---------------------------------------------------------------------------
in_align <= '1';
-- continue toggling and check that out_toggle aligns again
FOR I IN 0 TO c_interval-1 LOOP
in_toggle <= NOT in_toggle;
proc_common_wait_some_cycles(clk, c_half_period);
END LOOP;
---------------------------------------------------------------------------
-- stop in_toggle
---------------------------------------------------------------------------
proc_common_wait_some_cycles(clk, c_half_period*c_interval);
---------------------------------------------------------------------------
-- maintain after in_toggle has stopped
---------------------------------------------------------------------------
in_align <= '0';
proc_common_wait_some_cycles(clk, c_half_period*c_interval);
---------------------------------------------------------------------------
-- end
---------------------------------------------------------------------------
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
WAIT;
END PROCESS;
u_toggle : ENTITY work.common_toggle_align
GENERIC MAP (
g_pipeline => c_pipeline,
g_nof_clk_per_period => c_toggle_period
)
PORT MAP (
rst => rst,
clk => clk,
in_align => in_align,
in_toggle => in_toggle,
out_toggle => out_toggle
);
END tb;