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RTSD
HDL
Repository
b559785d3a23674eaf187faa8f462841b8921f02
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5
L2SDP-1106
L2SDP-LIFT
L2SDP-1113
master
default
protected
HPR-158
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hdl
libraries
technology
ddr
hdllib.cfg
hdllib.cfg
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10 years ago
7c4c80d1
Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixivdiff
· 7c4c80d1
Eric Kooistra
authored
10 years ago
7c4c80d1
History
Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixivdiff
Eric Kooistra
authored
10 years ago
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Eric Kooistra authoredEric Kooistra authored