tech_ddr_pkg.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;

PACKAGE tech_ddr_pkg IS  
  
  -- Gather all DDR parameters in one record
  TYPE t_c_tech_ddr IS RECORD
    -- PHY variant within a technology
    name                              : STRING(1 TO 4);  -- = "DDR3" or "DDR4"
    mts                               : NATURAL;  -- = 800   access rate in mega transfers per second
    master                            : BOOLEAN;  -- = TRUE  TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
    rank                              : STRING(1 TO 6);  -- = "SINGLE" or "DUAL  "
    -- PHY external FPGA IO
    a_w                               : NATURAL;  -- = 16
    a_row_w                           : NATURAL;  -- = 16     = a_w, row address width, via a_w lines
    a_col_w                           : NATURAL;  -- = 10    <= a_w, col address width, via a_w lines
    ba_w                              : NATURAL;  -- = 3
    dq_w                              : NATURAL;  -- = 64
    dqs_w                             : NATURAL;  -- = 8      = dq_w / nof_dq_per_dqs
    dm_w                              : NATURAL;  -- = 8
    dbi_w                             : NATURAL;  -- = 8
    bg_w                              : NATURAL;  -- = 2
    ck_w                              : NATURAL;  -- = 2
    cke_w                             : NATURAL;  -- = 2
    cs_w                              : NATURAL;  -- = 2      = number of chip select lines
    cs_w_w                            : NATURAL;  -- = 1      = true_log2(cs_w), use when the number of chip select lines is converted to a logical address
    odt_w                             : NATURAL;  -- = 2
    -- PHY internal FPGA IO
    terminationcontrol_w              : NATURAL;  -- = 14     internal bus in FPGA
    -- Controller
    rsl                               : NATURAL;  -- = 4      = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
    rsl_w                             : NATURAL;  -- = 2      = ceil_log2(rsl)
    command_queue_depth               : NATURAL;  -- = 8
    maxburstsize                      : NATURAL;  -- = 64
    maxburstsize_w                    : NATURAL;  -- = 7      = ceil_log2(maxburstsize+1)
  END RECORD;
      
  FUNCTION func_tech_sel_ddr(g_technology : NATURAL; g_ddr3, g_ddr4 : t_c_tech_ddr) RETURN t_c_tech_ddr;  -- Select DDR3 or DDR4 dependent on the technology
  FUNCTION func_tech_sel_ddr(g_sel        : BOOLEAN;      a,      b : t_c_tech_ddr) RETURN t_c_tech_ddr;  -- Select DDR dependent on the boolean
  
  FUNCTION func_tech_ddr_dq_address_w(  c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR address width for the DQ data at the PHY mts rate
  FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR address width for the controller data at the by rsl=4 reduced rate
  FUNCTION func_tech_ddr_ctlr_data_w(   c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR    data width for the controller data at the by rsl=4 reduced rate
  FUNCTION func_tech_ddr_module_size(   c_ddr : t_c_tech_ddr) RETURN NATURAL;  -- return DDR module size in GByte

  FUNCTION func_tech_ddr_sim_size(c_ddr : t_c_tech_ddr; sim_ctrl_addr_w : NATURAL) RETURN t_c_tech_ddr; -- derive sim_ddr from c_ddr (or alternatively use predefined c_tech_ddr*_sim)